search for: r25

...6 43741, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @int.array, i32 0, i64 2) ret void } The issue I have is this test is unnecessarily fragile because the compiler can (and recently has) decided to reorder the blocks in a perfectly valid way. For example: ; %bb.0: ldi r24, 221 ldi r25, 170 sts int.array+5, r25 sts int.array+4, r24 ldi r24, 204 ldi r25, 170 sts int.array+3, r25 sts int.array+2, r24 ldi r24, 187 ldi r25, 170 sts int.array+1, r25 sts int.array, r24 ret The three blocks should be independent, it doesn’t matter whether it does the store to array+5 and ar...

...t r20:r19 or r20:r18 would be invalid because the in the first case the low reg is odd and in the second case regs arent contiguous. To store data wider than 16 bits, for example for a 32 bit int we would use 2 register pairs (4 8bit regs) but here the pairs dont need to be contiguous so storing it r25:r24:r19:r18 is completely fine. As i said in my previous email this is achieved by using HARD_REGNO_MODE_OK in gcc. - Second, assuming the previous point works so the register constraints are done, how would i then proceed and combine two 8 bit instructions into a 16 bit one as Jeff pointed out in...

Hi Borja, > Without doing what i mentioned and letting LLVM expand all operations wider > than 8 bits as you asked, the code produced is excellent supposing that many > of the moves there should be 16 bit moves reducing code size and right > register allocation, also something important for me is that the code is > better than gcc's. When i say right reg allocation it doesnt

...explaining, Lang this example is exactly why i need the constraints and how to combine instructions. typedef short t; extern t mcos(t a); extern t mdiv(t a, t b); t foo(t a, t b) { short p1 = mcos(b); short p2 = mcos(a); return mdiv(p1&p2, p1^p2); } This C code produces: ; a<- r25:r24 b<--r23:r22 mov r18, r24 mov r19, r25 <-- can be combined into a movw r19:r18, r25:r24 mov r25, r23 mov r24, r22 <-- can be combined into a movw r25:r24, r23:r22 call mcos ; here we have the case i was explaining, pairs dont match because they'r...

...void >> } >> >> >> >> The issue I have is this test is unnecessarily fragile because the compiler can (and recently has) decided to reorder the blocks in a perfectly valid way. For example: >> ; %bb.0: >> ldi r24, 221 >> ldi r25, 170 >> sts int.array+5, r25 >> sts int.array+4, r24 >> ldi r24, 204 >> ldi r25, 170 >> sts int.array+3, r25 >> sts int.array+2, r24 >> ldi r24, 187 >> ldi r25, 17...

...bits is expanded into 8bit operations the 16bit instructions never get selected, also the reg allocator should allocate adjacent regs to form the pairs. The most important 16 bit instruction is data movement, this instruction can move register pairs in a single cycle, doing something like this: mov r25, r23 mov r24, r22 into: movw r25:r24, r23:r22 The key point here is that the movw instruction can only move data of fixed pairs in this way. movw Rdest+1:Rdest, Rorig+1:Rorig, so movw R25:R23, R21:R18 is illegal because registers pairs aren't adjacent. Explaining this as if it was for x86 may...

...you don't have a number of 16-bit instructions. [...] > typedef unsigned short t; > t foo(t a, t b, t c) > { > return a+b; > } [...] > This is fine until we get to the register allocation stage, there it does: > BB#0: derived from LLVM BB %entry > Live Ins: %R25R24 %R23R22 > %R18<def> = COPY %R24 > %R19<def> = COPY %R25 > %R24<def> = COPY %R22<kill>, %R25R24<imp-def> > %R24<def> = ADDRdRr %R24, %R18<kill>, %SREG<imp-def> > %R25<def> = COPY %R23<kill> > %R2...

...all result is collected in list format, but I am not able to get input there. Any help is really appreciated. esf.m <-foreach (i = 1:n.s, .combine=rbind) %dopar% { EV <- as.data.frame(eig$vectors[,1:n.candid[i]]) colnames(EV) <- paste("EV", 1:NCOL(EV), sep="") r25.esf.f <- lm(y ~ x1 + x2 +., data = EV) assign(paste("r25.esf.", i, sep=""), stepwise.forward(r25.esf.f, lm(y ~ x1 + x2, data = EV), 0.1, verbose = F))} -- View this message in context: http://r.789695.n4.nabble.com/parallel-processing-with-foreach-tp4647381.html Sent fro...

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi, Seeking suggestions to compute uncentered (pearson correlation) correlation efficiently. corr from stats library works on x and y columns. dist from amap library works on x and y rows. My data layout is slightly different such that row(i) of matrix x is compared to row(i) of matrix y. Thanks [[alternative HTML version deleted]]

Hi! Since linux-flashplugin7 r63 is vulnerable according to http://vuxml.FreeBSD.org/7c75d48c-429b-11db-afae-000c6ec775d9.html isn't www/linux-seamonkey vulerable, too (it seems to include 7 r25)? Bye Arne __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.

...ion1(i32, i32) Is being lowered to this assembly language... setServoAngle3: ; @setServoAngle3 ; %bb.0: ; %entry ldi r18, 119 ldi r19, 0 ldi r20, 0 ldi r21, 0 call myExternalFunction1 mov r18, r22 mov r19, r23 mov r22, r24 mov r23, r25 mov r24, r18 mov r25, r19 ret Which is clearly wrong. It should just be... setServoAngle3: ; @setServoAngle3 ; %bb.0: ; %entry ldi r18, 119 ldi r19, 0 ldi r20, 0 ldi r21, 0 call myExternalFunction1 ret The AVR ABI is based on the...

...what is > going on. > > This is the debug output i've got, some information is a bit cryptic for me so next is what i understood: ********** SIMPLE REGISTER COALESCING ********** ********** Function: foo ********** JOINING INTERVALS *********** entry: 16L %vreg0<def> = COPY %R25R24<kill>; DREGS:%vreg0 Considering merging %vreg0 with physreg %R25R24 RHS = %vreg0 = [16d,96d:0) 0 at 16d LHS = %R25R24,inf = [0L,16d:0) 0 at 0L-phidef updated: 96L %vreg8<def> = COPY %R25R24<kill>; PTRREGS:%vreg8 updated: 32L %vreg5&lt...

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Please review and comments. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops. Currently only ia64/xen pv_ops implementation

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Please review and comments. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops. Currently only ia64/xen pv_ops implementation