search for: r23

Hello, I am wondering whether there is a way to test whether two non-independent correlation coefficients are significantly different, in R? I have an experimentally measure variable Y, and two different variables X1, and X2, which are predictions of Y that were predicted using two different computational models. I would like to see whether the correlation of Y and X1, and Y and X2 is

...... rate10_max1 = ...... ......... so on.   ## ________________________________________________________   # PROBLEM - B   # Suppose Rij = ith Rate and jth range. (There are 3 ranges i.e. j= 3).   data_label = expand.grid(c("R11", "R12", "R13"), c("R21", "R23", "R23"))   # gives the output like     data_label      Var1        Var2 1    R11         R21 2    R12         R21 3    R13         R21 4    R11         R22 5    R12         R22 6    R13         R22 7    R11         R23 8    R12         R23 9    R13         R23                       ...

...l super reg interferes with sub reg instances, even though in reality they shouldn't conflict. That is, they are individual registers and would be better compared as such for register coalescing decisions (CoalescerPair::Partial = 0). For example, I have a super reg that has r20, r21, r22, and r23 physical registers. This super reg is the dest of a reg_sequence which generates 4 COPY MIs. The first COPY coalesces (merging into r20), but the vregs for r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that because doing so generates inteference on %vreg50, the "parent&...

...is expanded into 8bit operations the 16bit instructions never get selected, also the reg allocator should allocate adjacent regs to form the pairs. The most important 16 bit instruction is data movement, this instruction can move register pairs in a single cycle, doing something like this: mov r25, r23 mov r24, r22 into: movw r25:r24, r23:r22 The key point here is that the movw instruction can only move data of fixed pairs in this way. movw Rdest+1:Rdest, Rorig+1:Rorig, so movw R25:R23, R21:R18 is illegal because registers pairs aren't adjacent. Explaining this as if it was for x86 may make...

Revision: 23 Author: ajturner Date: Sun Aug 23 19:48:12 2009 Log: Changed build.xml to use correct directory slashes http://code.google.com/p/mapstraction/source/detail?r=23 Modified: /trunk/build.xml ======================================= --- /trunk/build.xml Sun Aug 16 17:18:10 2009 +++ /trunk/build.xml Sun Aug 23 19:48:12 2009 @@ -75,7 +75,7 @@ </path> <sequential>

Hi Borja, > Without doing what i mentioned and letting LLVM expand all operations wider > than 8 bits as you asked, the code produced is excellent supposing that many > of the moves there should be 16 bit moves reducing code size and right > register allocation, also something important for me is that the code is > better than gcc's. When i say right reg allocation it doesnt

...e, how would i then proceed and combine two 8 bit instructions into a 16 bit one as Jeff pointed out in his email? For example i want to combine a 16 bit add like this: // b = b + 1: (b stored in r25:r24) add r24, 1 adc r25, 0 into adw r25:r24, 1 and the one im talking all my mails about move r25, r23 move r24, r22 into movw r25:r24, r23:r22 or move r18, r2 move r19, r3 into movw r19:r18, r3:r2 any combination of moves with reg pairs are valid. I wrote a function pass to test, it scanned for moves and checked if next instruction was a move to see if globally it was a 16 move and replace those...

...this example is exactly why i need the constraints and how to combine instructions. typedef short t; extern t mcos(t a); extern t mdiv(t a, t b); t foo(t a, t b) { short p1 = mcos(b); short p2 = mcos(a); return mdiv(p1&p2, p1^p2); } This C code produces: ; a<- r25:r24 b<--r23:r22 mov r18, r24 mov r19, r25 <-- can be combined into a movw r19:r18, r25:r24 mov r25, r23 mov r24, r22 <-- can be combined into a movw r25:r24, r23:r22 call mcos ; here we have the case i was explaining, pairs dont match because they're the other way r...

...et. Here are some examples: - Some insns contain a 3-bit new value, the new value bits, Nv[2:1] are set to 1, 2, or 3 if the producer is 1, 2, or 3 insns ahead of the consumer. Nv[0] is 1 if the producer is an odd register, 0 for even. { r17 = add(r2, r17) r23 = add(r23, #-1) if (!cmp.eq(r23.new, #0)) jump:t foobar } The above packet has 2 producers, r17 and r23. If the compare and jump is encoded as: 0x2443e000 where new value bits are stored in [18:16] and equal 0x3 then register 23 would be used - Nv[2:1] == 0x1. The producer...

...g interferes with sub reg instances, even though in reality they shouldn't conflict. That is, they are individual registers and would be better compared as such for register coalescing decisions (CoalescerPair::Partial = 0). > > For example, I have a super reg that has r20, r21, r22, and r23 physical registers. This super reg is the dest of a reg_sequence which generates 4 COPY MIs. The first COPY coalesces (merging into r20), but the vregs for r21-r23 (SUPER_RC:%vreg50:subreg1..subreg3) are never coalesced after that because doing so generates inteference on %vreg50, the "parent&...

...collector, hopefully :). The fault occurs when I do: printf("process_root[0x%p] = 0x%p\n", (void*) Root, (void*) *Root); I.e, when I reference Root. My frontend creates llvm assembly with llvm-gcroot in the following manner: ... %r22 = alloca uint ;; typetagged integers/pointers %r23 = cast uint* %r22 to sbyte** call void %llvm.gcroot(sbyte** %r23, sbyte* null) ... So Root should be a valid pointer to the program stack. It traces two roots before the segmentation fault. Any ideas? Btw, can I run llvm-db with llvm assembly as source language? Haven't found any suitable...

...t; D2<-(lower(M2)) > D3<-(lower(M3)) > mantel(D1 ~ D2+D3, nperm=1000) mantelr pval1 pval2 pval3 llim.2.5% ulim.97.5% 0.09014696 0.10300000 0.89800000 0.18400000 0.01857311 0.18468621 > partial.mantel.test(M1,M2,M3,quiet=T) $MantelR r12 r13 r23 r12.3 r13.2 0.08977575 0.02170997 -0.01561346 0.09014696 0.02320821 $p [1] 0.09590410 0.30769231 0.47552448 0.09490509 0.30169830 $call [1] "partial.mantel.test(M1 = M1, M2 = M2, M3 = M3, quiet = T)" attr(,"class") [1] "partial.Mantel" > M1[1:10...

Hi Sid, This feels like it’s exposing too much of the disassembler internals into the MCOperand representation. I’m not sure I follow why that’s necessary. Can you elaborate a bit? -Jim On Jun 25, 2013, at 8:24 AM, Sid Manning <sidneym at codeaurora.org> wrote: > > I'm working on a disassembler for hexagon (vliw) architecture and I would like to add an additional operand type,

The PA-RISC ELF ABI puts the function pointer to be registered with atexit in %r23. Use this instead of passing in NULL. While it's unlikely to be used, doing the right thing is good. Signed-off-by: Kyle McMartin <kyle@parisc-linux.org> diff --git a/klibc/arch/parisc/crt0.S b/klibc/arch/parisc/crt0.S index 7428443..a9b6e96 100644 --- a/klibc/arch/parisc/crt0.S +++ b/k...

...'t have a number of 16-bit instructions. [...] > typedef unsigned short t; > t foo(t a, t b, t c) > { > return a+b; > } [...] > This is fine until we get to the register allocation stage, there it does: > BB#0: derived from LLVM BB %entry > Live Ins: %R25R24 %R23R22 > %R18<def> = COPY %R24 > %R19<def> = COPY %R25 > %R24<def> = COPY %R22<kill>, %R25R24<imp-def> > %R24<def> = ADDRdRr %R24, %R18<kill>, %SREG<imp-def> > %R25<def> = COPY %R23<kill> > %R25<def...

I'm working on a disassembler for hexagon (vliw) architecture and I would like to add an additional operand type, "kAux" to the MCOperand class. The reason for this is that each insn has parse bits which are not explicit operands and have differing meanings based on the insn's location within the packet and the number of insns inside the packet. In order for the disassembler

...declare i32 @myExternalFunction1(i32, i32) Is being lowered to this assembly language... setServoAngle3: ; @setServoAngle3 ; %bb.0: ; %entry ldi r18, 119 ldi r19, 0 ldi r20, 0 ldi r21, 0 call myExternalFunction1 mov r18, r22 mov r19, r23 mov r22, r24 mov r23, r25 mov r24, r18 mov r25, r19 ret Which is clearly wrong. It should just be... setServoAngle3: ; @setServoAngle3 ; %bb.0: ; %entry ldi r18, 119 ldi r19, 0 ldi r20, 0 ldi r21, 0 call myExternalFunction1 ret...

...a; p2 = p2 * b; p3 = p3 * c; p4 = p4 * d; } . . Compiling with NVCC, Ocelot, and LLVM, I can confirm the interleaved instruction schedule with a four-instruction reuse distance. An excerpt follows: . . %r1500 = fmul float %r1496, %r24 ; compute %1500 %r1501 = fmul float %r1497, %r23 %r1502 = fmul float %r1498, %r22 %r1503 = fmul float %r1499, %r21 %r1504 = fmul float %r1500, %r24 ; first use of %1500 %r1505 = fmul float %r1501, %r23 %r1506 = fmul float %r1502, %r22 %r1507 = fmul float %r1503, %r21 %r1508 = fmul float %r1504, %r24 ; first use of %1504 . ....

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place