Displaying 7 results from an estimated 7 matches for "r1r0".
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2010 Aug 29
2
[LLVMdev] Register design decision for backend
...pairs inside
another regclass of size i16, marking the pairs as subregs of the 8bit regs
this way:
<stripped version of my code)>
// 8 bit regs
def R0 : Register<"r0">, DwarfRegNum<[0]>;
def R1 : Register<"r1">, DwarfRegNum<[1]>;
// reg pairs
def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>;
def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>;
def WDREGS : RegisterClass<"TEST", [i16], 16, [R1R0]>
{
let SubRegClassList = [GPR8, GPR8];
}
This way i could work with registe...
2010 Aug 31
0
[LLVMdev] Register design decision for backend
...ing the pairs as subregs of the 8bit regs
> this way:
>
> <stripped version of my code)>
>
> // 8 bit regs
> def R0 : Register<"r0">, DwarfRegNum<[0]>;
> def R1 : Register<"r1">, DwarfRegNum<[1]>;
>
> // reg pairs
> def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>;
>
> def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>;
> def WDREGS : RegisterClass<"TEST", [i16], 16, [R1R0]>
> {
> let SubRegClassList = [GPR8, GPR8];
> }
>
&...
2010 Aug 31
2
[LLVMdev] Register design decision for backend
...eply to my question :)
I got a bit confused with the fact you said that the subregister class is
larger than the superregister class. As far as i understood or what i tried
to do with my code is to define a register pair composed of two 8 bit
registers the way i described in my previous message. So R1R0 in WDREGS is
directly mapped into R0 and R1 of GPR8. Meaning that 2 GPR8 = 1 WDREG. Also,
R1R0 is the superreg of R1 and R0?
Incase i wasnt clear enough i'll expose a simple example using the common
known x86 arch.
AX is composed by AL and AH (AX and AH are subregs of AX), now assume x86
can o...
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
Hello Jakob, thanks for the reply. The three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:
DREGS: R31R30, R29R28 down to R1R0 (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
PTRREGS: R31R30, R29R28, R27R26 (3 regs)
All classes intersect each other giving as a result the smaller class:
DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the
coalescer should work sinc...
2011 Mar 26
0
[LLVMdev] Possible missed optimization?
On Mar 24, 2011, at 5:42 PM, Borja Ferrer wrote:
> The last copy instruction should be removed as pointed out above, but since R27R26 is killed in the load instruction it has to be emitted. About the insane amount of regclasses there, the load/store and the andi instructions take subsets of regs from the main register class, they cant work with all registers, that's why STW and LDW needs
2011 Mar 25
2
[LLVMdev] Possible missed optimization?
Hello, I've noticed the following issue while testing some codegen tests, i
would like to know if it's a missed optimization or i missed something out
here. This is for an out of tree backend im writing. I managed to reduce it
to the following C function:
void foo(int *a) // int here is 16bits
{
*a &= 0xFF;
}
This is the code before regalloc:
Live Ins: %R25R24
2011 Mar 26
0
[LLVMdev] Possible missed optimization?
...ar 26, 2011, at 1:04 PM, Borja Ferrer wrote:
> Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean:
>
> DREGS: R31R30, R29R28 down to R1R0 (16 regs)
> DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
> PTRREGS: R31R30, R29R28, R27R26 (3 regs)
>
> All classes intersect each other giving as a result the smaller class: DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the coales...