Displaying 3 results from an estimated 3 matches for "r1_i".
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2005 Apr 20
1
[LLVMdev] adding new instructions to support "swizzle" and "writemask"
Hello, everyone:
I am writing a compiler for a programmable graphics hardware. Each
registers of the hardware has four channels, namely 'r', 'b', 'g',
'a', and each channel is a 32-bit floating point. It's similar to the
high and low 8-bit of an x86 16-bit general purpose register "AX" can
be individually referenced as "AH" and
2005 May 06
3
[LLVMdev] avoid live range overlap of "vector" registers
a "vector" register r0 is composed of four 32-bit floating scalar
registers, r0.x, r0.y, r0.z, r0.w.
each scalar reg can be assigned individually, e.g.
mov r0.x, r1.y
add r0.y, r1,x, r2.z
or assigned simultaneously with vector instructions, e.g.
add r0.xyzw, r1.xzyw, r2.xyzw
My question is how to define the register in .td file to avoid the
code generator overlaps the
2005 May 10
0
[LLVMdev] avoid live range overlap of "vector" registers
On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> a "vector" register r0 is composed of four 32-bit floating scalar
> registers, r0.x, r0.y, r0.z, r0.w.
>
> each scalar reg can be assigned individually, e.g.
>
> mov r0.x, r1.y
> add r0.y, r1,x, r2.z
>
> or assigned simultaneously with vector instructions, e.g.
>
> add r0.xyzw, r1.xzyw, r2.xyzw
>
> My