Displaying 2 results from an estimated 2 matches for "r1_bia".
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r1_bias
2005 Jul 27
3
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
Each register is a 4-component (namely, r, g, b, a) vector register.
They are actually defined as llvm packed [4xfloat].
The instruction:
add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz
Explaination:
'.a' is a writemask. only the specified component will be update
'.xxyy' and '.zzzz' are swizzle masks, specify the component
permutation, simliar to the Intel SSE permutation instruction SHUFPD
'_bias' and '_x2' are modifi...
2005 Jul 29
0
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
...ion selector to
recognise the shuffle+add combination and emit a single instruction.
m.
Tzu-Chien Chiu wrote:
> Each register is a 4-component (namely, r, g, b, a) vector register.
> They are actually defined as llvm packed [4xfloat].
>
> The instruction:
>
> add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz
>
> Explaination:
>
> '.a' is a writemask. only the specified component will be update
>
> '.xxyy' and '.zzzz' are swizzle masks, specify the component
> permutation, simliar to the Intel SSE permutation instruction SHUFPD
>
>...