search for: r19

...$2, 12($fp) or $1, $2, $1 sltiu $2, $1, 1 move $sp, $fp lw $fp, 20($sp) addiu $sp, $sp, 24 jr $ra nop The two comparisons are very similar. For the Microblaze, I get: signed long long: main: .frame r19,40,r15 .mask 0x80000 addik r1, r1, -40 swi r19, r1, 4 add r19, r1, r0 swi r0, r19, 8 addik r3, r0, 100 swi r3, r19, 20 swi r0, r19, 16 addik r3, r0, -2147483648 swi...

...6 bit data in two contiguous 8 bit regs being the low part an even reg? Remember data would be expanded into 8 bit ops, so when we're working with dags after type legalization do we really know the original type before expansion? As an example, storing a short in r21:r20 would be valid, but r20:r19 or r20:r18 would be invalid because the in the first case the low reg is odd and in the second case regs arent contiguous. To store data wider than 16 bits, for example for a 32 bit int we would use 2 register pairs (4 8bit regs) but here the pairs dont need to be contiguous so storing it r25:r24:r...

Hi Borja, > Without doing what i mentioned and letting LLVM expand all operations wider > than 8 bits as you asked, the code produced is excellent supposing that many > of the moves there should be 16 bit moves reducing code size and right > register allocation, also something important for me is that the code is > better than gcc's. When i say right reg allocation it doesnt

...6) + stw %r10,32(%r26) + stw %r11,36(%r26) + stw %r12,40(%r26) + stw %r13,44(%r26) + stw %r14,48(%r26) + stw %r15,52(%r26) + stw %r16,56(%r26) + stw %r17,60(%r26) + stw %r18,64(%r26) + stw %r19,68(%r26) + stw %r27,72(%r26) + stw %r30,76(%r26) + stw %rp,80(%r26) + ldo 88(%r26),%r19 + fstd,ma %fr12,8(%r19) + fstd,ma %fr13,8(%r19) + fstd,ma %fr14,8(%r19) + fstd,ma %fr15,8(%r19) + fstd,ma %fr16,8(%r19) + fst...

...constraints and how to combine instructions. typedef short t; extern t mcos(t a); extern t mdiv(t a, t b); t foo(t a, t b) { short p1 = mcos(b); short p2 = mcos(a); return mdiv(p1&p2, p1^p2); } This C code produces: ; a<- r25:r24 b<--r23:r22 mov r18, r24 mov r19, r25 <-- can be combined into a movw r19:r18, r25:r24 mov r25, r23 mov r24, r22 <-- can be combined into a movw r25:r24, r23:r22 call mcos ; here we have the case i was explaining, pairs dont match because they're the other way round, function result is in r25:r24 ; b...

...lk dovecot: POP3(obec at nizkov.cz): Mailbox init failed top=0/0, retr=0/0, del=0/0, size=0 Feb 1 14:42:44 vlk dovecot: POP3(obec at nizkov.cz): mbox sync: UID inserted in the middle of mailbox /var/mail/obec at nizkov.cz (68386 > 68346, seq=2, idx_msgs=3) this is on FreeBSD at i386 runnin 1.0.r19 (but I have seen this with all versions of 1.0.x), filesystem in use is UFS (ie. local filesystem). THe mailing client in question seems to be outlook express. I can provide the mbox in question. locking method is #lock_method = flock and the dovecot was compiled with kqueue thnx roman

...mber, %rp contains whence we came, + * %rp is saved and restored across the syscall, thankfully. + * + */ + + .text + .align 64 ; cache-width aligned + .globl vfork + .type vfork, at function +vfork: + /* pid_t vfork(void) */ + ble 0x100(%sr2, %r0) ; jump to gateway page + nop + + ldi -0x1000,%r19 ; %r19 = -4096 + sub %r0,%ret0,%r22 ; %r22 = -%ret0 + cmpb,>>=,n %r19,%ret0,1f ; if %ret0 >= -4096UL + ldi -1,%ret0 ; nullified on taken forward + + /* store %r22 to errno... */ + ldil L%errno,%r1 + ldo R%errno(%r1),%r1 + stw %r22,0(%r1) +1: + bv %r0(%rp) ; jump back + nop + + ....

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

...gt; typedef unsigned short t; > t foo(t a, t b, t c) > { > return a+b; > } [...] > This is fine until we get to the register allocation stage, there it does: > BB#0: derived from LLVM BB %entry > Live Ins: %R25R24 %R23R22 > %R18<def> = COPY %R24 > %R19<def> = COPY %R25 > %R24<def> = COPY %R22<kill>, %R25R24<imp-def> > %R24<def> = ADDRdRr %R24, %R18<kill>, %SREG<imp-def> > %R25<def> = COPY %R23<kill> > %R25<def> = ADCRdRr %R25, %R19<kill>, %SREG<imp-de...

...NE INTO REG PAIR AGAIN %R25R24<def> = COPY %reg16393; WDREGS:%reg16393 // COPY REG PAIR INTO RETURN REG. RET This is fine until we get to the register allocation stage, there it does: BB#0: derived from LLVM BB %entry Live Ins: %R25R24 %R23R22 %R18<def> = COPY %R24 %R19<def> = COPY %R25 %R24<def> = COPY %R22<kill>, %R25R24<imp-def> %R24<def> = ADDRdRr %R24, %R18<kill>, %SREG<imp-def> %R25<def> = COPY %R23<kill> %R25<def> = ADCRdRr %R25, %R19<kill>, %SREG<imp-def,dead>, %SREG&lt...

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Author: tha-guest Date: 2006-02-18 16:38:52 +0000 (Sat, 18 Feb 2006) New Revision: 19 Modified: trunk/debian/control trunk/debian/patches/00list trunk/debian/rules trunk/debian/xen-hypervisor-pae.install trunk/debian/xen-hypervisor.install Log: - changed debian/rules to build a pae hypervisor on i386 (has to be done after the "make dist" for the non-pae stuff) - changed

...Sparc, Microblaze, and Mips code generators implement branch delay slots. They all seem to exhibit the same bug, which is not surprising since the code is very similar. If I compile code with this snippit: while (n--) *s++ = (char) c; I get this (for the Microblaze): swi r19, r1, 0 add r3, r0, r0 cmp r3, r3, r7 beqid r3, ($BB0_3) brid ($BB0_1) add r19, r1, r0 add r3, r5, r0 $BB0_2: addi r4, r3, 1 addi r7, r7, -1 add r8, r0, r0 sbi...

...mmon + .type __syscall_common,@function +__syscall_common: + ldo 0x40(%sp),%sp + stw %rp,-0x54(%sp) ; save return pointer + + ldw -0x74(%sp),%r22 ; %arg4 + ldw -0x78(%sp),%r21 ; %arg5 + + ble 0x100(%sr2, %r0) ; jump to gateway page + nop ; can we move a load here? + + ldi -0x1000,%r19 ; %r19 = -4096 + sub %r0,%ret0,%r22 ; %r22 = -%ret0 + cmpb,>>=,n %r19,%ret0,1f ; if %ret0 >= -4096UL + ldi -1,%ret0 ; nullified on taken forward + + /* store %r22 to errno... */ + ldil L%errno,%r1 + ldo R%errno(%r1),%r1 + stw %r22,0(%r1) +1: + ldw -0x54(%sp),%rp ; restore retur...

...about 2 minutes before dropping it. The FXO is attached to a key system (hybrid PBX). There was a home-type digital answering machine previously on the same extension and it was able to sense disconnect without any problems. The interface is a non-Digium single port FXO card (modem) with R13 & R19 removed to mimic the Digium card. The software is the current release of Asterisk@home from ISO format (self booting CD that does an OS install and Asterisk compile automagically). My question is if Asterisk has settings to control disconnect sense, or do I have to look at the key system (hybrid P...

...addr { entry: %1 = call i32 @myExternalFunction1(i32 %0, i32 119) ret i32 %1 } declare i32 @myExternalFunction1(i32, i32) Is being lowered to this assembly language... setServoAngle3: ; @setServoAngle3 ; %bb.0: ; %entry ldi r18, 119 ldi r19, 0 ldi r20, 0 ldi r21, 0 call myExternalFunction1 mov r18, r22 mov r19, r23 mov r22, r24 mov r23, r25 mov r24, r18 mov r25, r19 ret Which is clearly wrong. It should just be... setServoAngle3: ; @setServoAngle3 ; %bb.0: ; %entry ld...

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.