search for: r182701

Displaying 1 result from an estimated 1 matches for "r182701".

Did you mean: 1182701
2013 May 26
0
[LLVMdev] SelectionDAG Preserves IR Order
...A-sched=source now works the way it was meant to. This means I can effectively bypass the SelectionDAG scheduler and enable the MachineScheduler. Otherwise MachineScheduler would have to correct any havoc wrought by SD scheduler, which it is not designed to do. I committed Xiaoyi's patches as: r182701,r182703,r182704,182706. Beware that out-of-tree targets will see merge conflicts in <Tgt>ISelDAGToDAG.cpp and <Tgt>ISelLowering.cpp. These should be trivial to resolve with a regex replace something like this: 's/DebugLoc dl = ([^.]+)\.getNode\(\)->getDebugLoc\(\)/SDLoc dl(\1)/...