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2010 Nov 18
1
[LLVMdev] subregs in trivial coalescing
...b1 are 64-bit subregs and sub0/1/2/3 are 32 bit subregs. DEF64 is just representative of a 64 bit ALU operation. The code is correct at this point. Q1 (a 128-bit physical register) is assigned to %reg16402 which is ok but then RALinScan::attemptTrivialCoalescing thinks it can coalesce r16405 with r16402 giving: 92L Q1:dsub0<def> = DEF64 %reg16402<imp-def>, QPR:%reg16402 116L Q1:sub0<def> = COPY Q1:sub1, %reg16405<imp-def>; QPR:%reg16405,16402 124L %reg16413:sub0<def> = COPY Q1:sub0; QPR:%reg16413,16405 .... stuff .... 468L %reg16460:sub3<def> =...