Displaying 2 results from an estimated 2 matches for "r158380".
2012 Jun 13
0
[LLVMdev] Latency of true depency of store followed by aliased load in ScheduleDAGInstrs
...ycle as
> the store. Is ScheduleDAGInstrs incorrect in the volatile case or
> shouldn't I rely on the latency being non zero for getting a correct
> schedule?
I don't like the inconsistency. There's no reason for it other than sloppy implementation. I tried to clean this up in r158380. Memory dependence latency should now be conservative in this respect.
That said, this was really meant to be a heuristic, and a fairly unimportant one at that, so I never paid much attention to the inconsistency. Whether memory dependencies can be bundled in the same group is cpu specific. Regist...
2012 Jun 12
2
[LLVMdev] Latency of true depency of store followed by aliased load in ScheduleDAGInstrs
Hi all,
I have a question regarding the latency of the true dependency of a
store followed by an aliased load in ScheduleDAGInstrs. The latency
seems to depend on the store and load being volatile or not as can be
seen in the post-RA-sched debug output of the attached ARM example:
$ llc -O3 -debug-only=post-RA-sched store_load_latency_test.ll
...
SU(2): STRi12 %R2<kill>,