Displaying 20 results from an estimated 41 matches for "r14d".
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2015 Feb 13
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...push r13
push r12
push rbx
sub rsp, 18h
mov ebx, 0FFFFFFFFh
cmp edi, 2
jnz loc_100000F29
mov rdi, [rsi+8] ; char *
xor r14d, r14d
xor esi, esi ; char **
mov edx, 0Ah ; int
call _strtol
mov r15, rax
shl rax, 20h
mov rsi, offset __mh_execute_header
add rsi, rax...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...t; push rbx
>> sub rsp, 18h
>> mov ebx, 0FFFFFFFFh
>> cmp edi, 2
>> jnz loc_100000F29
>> mov rdi, [rsi+8] ; char *
>> xor r14d, r14d
>> xor esi, esi ; char **
>> mov edx, 0Ah ; int
>> call _strtol
>> mov r15, rax
>> shl rax, 20h
>> mov rsi, offset __mh_exec...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...sub rsp, 18h
>>>> mov ebx, 0FFFFFFFFh
>>>> cmp edi, 2
>>>> jnz loc_100000F29
>>>> mov rdi, [rsi+8] ; char *
>>>> xor r14d, r14d
>>>> xor esi, esi ; char **
>>>> mov edx, 0Ah ; int
>>>> call _strtol
>>>> mov r15, rax
>>>> shl rax, 20h
>>>&g...
2019 Nov 08
2
Register Dataflow Analysis on X86
Do you know whether it has been fixed on the 8.0.1 release?
Scott
On Fri, Nov 8, 2019 at 9:45 AM Krzysztof Parzyszek <kparzysz at quicinc.com<mailto:kparzysz at quicinc.com>> wrote:
The one blocking issue that existed in the past has been fixed. I haven’t had time to do any work on it lately, but I’m not aware of any fundamental problems that would make it not work on x86.
--
2009 Dec 07
4
[LLVMdev] 2.6 JIT using wrong address for external functions
...0i 0xfffffd7ff9302528
0xfffffd7ff9302528: push %r14
0xfffffd7ff930252a: push %rbx
0xfffffd7ff930252b: sub $0x18,%rsp
0xfffffd7ff930252f: test %rdx,%rdx
0xfffffd7ff9302532: jne 0xfffffd7ff9302747
0xfffffd7ff9302538: mov %rdi,%rbx
0xfffffd7ff930253b: xor %r14d,%r14d
0xfffffd7ff930253e: mov $0x2d6,%edx
0xfffffd7ff9302543: mov %rbx,%rdi
0xfffffd7ff9302546: mov %r14d,%esi
>>> 0xfffffd7ff9302549: callq 0xfffffd800066f690
0xfffffd7ff930254e: cvtsi2sd %rax,%xmm0
0xfffffd7ff9302553: mov $0xfffffd7ff93024d0,%rax
0xff...
2019 Dec 23
2
Register Dataflow Analysis on X86
...P>(d427,b1009):u1011, u1101<EBP>(d427,b1027):u1029]
p1102: phi [+d1103<R13D>(,,u1075):, u1104<R13D>(d557,b477):u563, u1105<R13D>(d411,b448):, u1106<R13D>(d411,b462):u459, u1107<R13D>(d411,b1009):u1106, u1108<R13D>(d411,b1027):u1107]
p1109: phi [+d1110<R14D>(,d625,u612):, u1111<R14D>(d584,b477):, u1112<R14D>(d452,b448):, u1113<R14D>(d466,b462):, u1114<R14D>(d1013,b1009):, u1115<R14D>(d1031,b1027):]
p1116: phi [+d1117<#1073741833>(,d645,u648):, u1118"<#1073741833>(d579,b477):, u1466"<#1073741833...
2020 Jan 10
2
Register Dataflow Analysis on X86
...P>(d427,b1009):u1011, u1101<EBP>(d427,b1027):u1029]
p1102: phi [+d1103<R13D>(,,u1075):, u1104<R13D>(d557,b477):u563, u1105<R13D>(d411,b448):, u1106<R13D>(d411,b462):u459, u1107<R13D>(d411,b1009):u1106, u1108<R13D>(d411,b1027):u1107]
p1109: phi [+d1110<R14D>(,d625,u612):, u1111<R14D>(d584,b477):, u1112<R14D>(d452,b448):, u1113<R14D>(d466,b462):, u1114<R14D>(d1013,b1009):, u1115<R14D>(d1031,b1027):]
p1116: phi [+d1117<#1073741833>(,d645,u648):, u1118"<#1073741833>(d579,b477):, u1466"<#1073741833...
2016 Jun 30
4
Help required regarding IPRA and Local Function optimization
...code :
define void @bar() #0 {
call void asm sideeffect "movl %ecx, %r15d", "~{r15}"() #0
call void @foo()
call void asm sideeffect "movl %r15d, %ebx", "~{rbx}"() #0
ret void
}
define internal void @foo() #0 {
call void asm sideeffect "movl %r14d, %r15d", "~{r15}"() #0
ret void
}
and its generated assembly code when IPRA enabled:
.section __TEXT,__text,regular,pure_instructions
.macosx_version_min 10, 12
.p2align 4, 0x90
_foo: ## @foo
.cfi_startproc
## BB#0:
## InlineAsm Start
movl %r14d,...
2015 Mar 30
0
[Bug 82714] [G84] nouveau fails to properly initialize GPU
...mov %rbx,-0x20(%rbp)
18c: 4c 89 75 f8 mov %r14,-0x8(%rbp)
190: 48 89 fb mov %rdi,%rbx
193: 4c 89 65 e8 mov %r12,-0x18(%rbp)
197: 4c 89 6d f0 mov %r13,-0x10(%rbp)
19b: 41 89 f6 mov %esi,%r14d
19e: 48 8b 47 08 mov 0x8(%rdi),%rax
1a2: 48 8b 78 40 mov 0x40(%rax),%rdi
1a6: 48 85 ff test %rdi,%rdi
1a9: 0f 84 e1 00 00 00 je 290 <evo_wait+0x110>
1af: e8 00 00 00 00 callq 1b4 <evo_wait+0x34...
2009 Dec 07
0
[LLVMdev] 2.6 JIT using wrong address for external functions
...7ff9302528: push %r14
> 0xfffffd7ff930252a: push %rbx
> 0xfffffd7ff930252b: sub $0x18,%rsp
> 0xfffffd7ff930252f: test %rdx,%rdx
> 0xfffffd7ff9302532: jne 0xfffffd7ff9302747
> 0xfffffd7ff9302538: mov %rdi,%rbx
> 0xfffffd7ff930253b: xor %r14d,%r14d
> 0xfffffd7ff930253e: mov $0x2d6,%edx
> 0xfffffd7ff9302543: mov %rbx,%rdi
> 0xfffffd7ff9302546: mov %r14d,%esi
>>>> 0xfffffd7ff9302549: callq 0xfffffd800066f690
> 0xfffffd7ff930254e: cvtsi2sd %rax,%xmm0
> 0xfffffd7ff9302553: mov ...
2018 Feb 06
3
What does a dead register mean?
...gram I see the following
sequence:
ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead
%eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp
CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx %r12
%r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d %r12w %r13w
%r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def %rsp,
implicit-def %ssp
ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead %eflags,
implicit-def dead %ssp, implicit %rsp, implicit %ssp
RET 0
The ADJCALLSTACKDOWN64 has implicit-def dead %rsp. However t...
2016 Jun 30
0
Help required regarding IPRA and Local Function optimization
...shq %rbx
0x10001950d <+13>: pushq %rax
0x10001950e <+14>: movl %ecx, %r12d
0x100019511 <+17>: movl %edx, %r13d
0x100019514 <+20>: movl %esi, %r15d
0x100019517 <+23>: movq %rdi, %rbx
-> 0x10001951a <+26>: movl 0x18(%rbx), %r14d
Please correct me if any thing is wrong and also please provide some help.
-Vivek
2016-06-30 14:21 GMT+05:30 vivek pandya <vivekvpandya at gmail.com>:
> Hello Mentors,
>
> I am currently finding bug in Local Function related optimization due to
> which runtime failures are obs...
2015 Jul 13
5
[LLVMdev] Poor register allocations vs gcc
..._custom -std=c11 -O3 -march=native -c app2.c -S
Versions (latest for each, downloaded just a few days ago):
gcc : 5.1
clang/llvm: clang+llvm-3.6.1-x86_64-apple-darwin
Host:
osx yosemite.
The assembly (cut to the essential):
LLVM:
pushq %rbp
movq %rsp, %rbp
pushq %r14
pushq %rbx
movl %edi, %r14d
leal 71(%r14), %eax
xorl %ecx, %ecx
cmpl $56, %eax
movl $92, %ebx
cmovnel %ecx, %ebx
leaq L_.str(%rip), %rdi
callq _puts
leal 71(%rbx,%r14), %eax
popq %rbx
popq %r14
popq %rbp
retq
and the gcc one:
pushq %rbp
movl $0, %eax
movl $92, %ebp
pushq %rbx
leal 71(%rdi), %ebx
lea...
2013 Sep 12
1
[LLVMdev] bug in X86 disasm code?
...\
ENTRY(EBX) \
ENTRY(sib) \
ENTRY(EBP) \
ENTRY(ESI) \
ENTRY(EDI) \
ENTRY(R8D) \
ENTRY(R9D) \
ENTRY(R10D) \
ENTRY(R11D) \
ENTRY(R12D) \
ENTRY(R13D) \
ENTRY(R14D) \
ENTRY(R15D)
the ENTRY(sib) looks suspicious. that should be ENTRY(ESP), no?
thanks.
J
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2017 Sep 29
2
HiPE calling convention
...55 push %r13
5e57: 41 54 push %r12
5e59: 53 push %rbx
5e5a: 48 83 ec 58 sub $0x58,%rsp
5e5e: 31 db xor %ebx,%ebx
5e60: 45 31 f6 xor %r14d,%r14d
5e63: 66 66 66 66 2e 0f 1f data16 data16 data16 nopw
%cs:0x0(%rax,%rax,1)
5e6a: 84 00 00 00 00 00
5e70: 4c 89 34 24 mov %r14,(%rsp)
5e74: 48 89 5c 24 08 mov %rbx,0x8(%rsp)
5e79: 4c 8b 3c 24 mov (%rs...
2016 Jun 25
3
Tail call optimization is getting affected due to local function related optimization with IPRA
...collected by RegUsageInfoCollector pass.
Function Name : bitrv2
Clobbered Registers:
AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI ESP
RAX
RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B R9B
R10B
R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W R10W
R11W
R12W R13W R14W R15W
How ever caller of bitrv2, makewt has callee saved registers as per CC, but
this
code results in segmentation fault when compliled with O1 because makewt
has value
of *ip in R14 register and that is stored and restore by makewt at begining
of call
but due...
2018 Feb 06
0
What does a dead register mean?
...quence:
>
> ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead
> %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp
> CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx
> %r12 %r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d
> %r12w %r13w %r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def
> %rsp, implicit-def %ssp
> ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead
> %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp
> RET 0
>
>
> The ADJCALLSTACKD...
2015 Jul 13
2
[LLVMdev] Poor register allocations vs gcc
...gt;<br />šHost:<br />šosx yosemite.<br /><br />šThe assembly (cut to the essential):<br /><br />šLLVM:<br />šššššššššpushq %rbp<br />šššššššššmovq %rsp, %rbp<br />šššššššššpushq %r14<br />šššššššššpushq %rbx<br />šššššššššmovl %edi, %r14d<br />šššššššššleal 71(%r14), %eax<br />šššššššššxorl %ecx, %ecx<br />šššššššššcmpl $56, %eax<br />šššššššššmovl $92, %ebx<br />šššššššššcmovnel %ecx, %ebx<br />šššššššššleaq L_.str(%rip), %rdi<br />šššššššššcallq _puts<br />šššššššššleal 71(%rbx,%r14)...
2016 Jun 27
3
Finding caller-saved registers at a function call site
...i.e., storage location rbp - 0x8) is used
in the addition to calculate the returned value. However, when I print the
RegMask operand for the call machine instruction, I get the following:
<regmask %BH %BL %BP %BPL %BX %EBP %EBX %RBP %RBX %R12 %R13 %R14 %R15 %R12B
%R13B %R14B %R15B %R12D %R13D %R14D %R15D %R12W %R13W %R14W %R15W>
I don't see xmm1 as being preserved across this call. Am I missing
something? Thanks for your help!
On Wed, Jun 22, 2016 at 5:01 PM, Sanjoy Das <sanjoy at playingwithpointers.com>
wrote:
> Hi Rob,
>
> Rob Lyerly via llvm-dev wrote:
> >...
2011 Mar 19
2
[LLVMdev] Apparent optimizer bug on X86_64
...:
1300 /*-----------------------------.
1301 | yyreduce -- Do a reduction. |
1302 `-----------------------------*/
1303 yyreduce:
1304 /* yyn is the number of a rule to reduce with. */
1305 yylen = yyr2[yyn];
0x0000000000400c14 <rpcalc_parse+628>: mov r15d,r14d
0x0000000000400c17 <rpcalc_parse+631>: movzx r12d,BYTE PTR
[r15+0x4015e2]
0x0000000000400c1f <rpcalc_parse+639>: mov eax,0x1
0x0000000000400c24 <rpcalc_parse+644>: mov r13,rax
0x0000000000400c27 <rpcalc_parse+647>: sub r13,r12...