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2019 Nov 08
2
Register Dataflow Analysis on X86
Do you know whether it has been fixed on the 8.0.1 release? Scott On Fri, Nov 8, 2019 at 9:45 AM Krzysztof Parzyszek <kparzysz at quicinc.com<mailto:kparzysz at quicinc.com>> wrote: The one blocking issue that existed in the past has been fixed. I haven’t had time to do any work on it lately, but I’m not aware of any fundamental problems that would make it not work on x86. --
2019 Dec 23
2
Register Dataflow Analysis on X86
...bb.24, %bb.20, %bb.22, %bb.49, %bb.52 succs(2): %bb.18, %bb.37 p1095: phi [+d1096<EBP>(,d668,):, u1097<EBP>(d540,b477):u555, u1098<EBP>(d427,b448):u450, u1099<EBP>(d427,b462):u464, u1100<EBP>(d427,b1009):u1011, u1101<EBP>(d427,b1027):u1029] p1102: phi [+d1103<R13D>(,,u1075):, u1104<R13D>(d557,b477):u563, u1105<R13D>(d411,b448):, u1106<R13D>(d411,b462):u459, u1107<R13D>(d411,b1009):u1106, u1108<R13D>(d411,b1027):u1107] p1109: phi [+d1110<R14D>(,d625,u612):, u1111<R14D>(d584,b477):, u1112<R14D>(d452,b448):, u1...
2016 Jul 06
3
IPRA, interprocedural register allocation, question
...on Divisor using Euclid's Algorithm */ __asm__ __volatile__ ( "movl %1, %%r15d;" "movl %2, %%ecx;" "CONTD: cmpl $0, %%ecx;" "je DONE;" "xorl %%r13d, %%r13d;" "idivl %%ecx;" "movl %%ecx, %%r15d;" "movl %%r13d, %%ecx;" "jmp CONTD;" "DONE: movl %%r15d, %0;" : &quot...
2020 Jan 10
2
Register Dataflow Analysis on X86
...bb.24, %bb.20, %bb.22, %bb.49, %bb.52 succs(2): %bb.18, %bb.37 p1095: phi [+d1096<EBP>(,d668,):, u1097<EBP>(d540,b477):u555, u1098<EBP>(d427,b448):u450, u1099<EBP>(d427,b462):u464, u1100<EBP>(d427,b1009):u1011, u1101<EBP>(d427,b1027):u1029] p1102: phi [+d1103<R13D>(,,u1075):, u1104<R13D>(d557,b477):u563, u1105<R13D>(d411,b448):, u1106<R13D>(d411,b462):u459, u1107<R13D>(d411,b1009):u1106, u1108<R13D>(d411,b1027):u1107] p1109: phi [+d1110<R14D>(,d625,u612):, u1111<R14D>(d584,b477):, u1112<R14D>(d452,b448):, u1...
2015 Feb 13
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...nop word ptr [rax+rax+00000000h] loc_100000E20: ; CODE XREF: _main+216 j test r15d, r15d setle cl cmp r15d, 2 jl short loc_100000E90 test cl, cl mov r13d, 0 mov r11, r12 mov r10d, 1 jnz short loc_100000E90 loc_100000E3F: ; CODE XREF: _main+1F0 j mov edi, [rax+r13*4] mov edx, 0FFFFFFFFh mov ecx, 1...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...0: ; CODE XREF: _main+216 j >> test r15d, r15d >> setle cl >> cmp r15d, 2 >> jl short loc_100000E90 >> test cl, cl >> mov r13d, 0 >> mov r11, r12 >> mov r10d, 1 >> jnz short loc_100000E90 >> >> loc_100000E3F: ; CODE XREF: _main+1F0 j >> mov edi, [rax+r13*4] >> mo...
2016 Jul 08
2
IPRA, interprocedural register allocation, question
...t; __asm__ __volatile__ ( "movl %1, %%r15d;" > > "movl %2, %%ecx;" > > "CONTD: cmpl $0, %%ecx;" > > "je DONE;" > > "xorl %%r13d, %%r13d;" > > "idivl %%ecx;" > > "movl %%ecx, %%r15d;" > > "movl %%r13d, %%ecx;" > > "jmp CONTD;" > >...
2015 Feb 14
2
[LLVMdev] trunk's optimizer generates slower code than 3.5
...16 j >>>> test r15d, r15d >>>> setle cl >>>> cmp r15d, 2 >>>> jl short loc_100000E90 >>>> test cl, cl >>>> mov r13d, 0 >>>> mov r11, r12 >>>> mov r10d, 1 >>>> jnz short loc_100000E90 >>>> >>>> loc_100000E3F: ; CODE XREF: _main+1F0 j >>>> mov...
2016 Jun 16
2
[PATCH v7 00/12] Support non-lru page migration
...lea 0x78(%r12),%r14 > 6384: 4c 89 ee mov %r13,%rsi > 6387: 4c 89 e7 mov %r12,%rdi > 638a: e8 86 c7 ff ff callq 2b15 <get_first_obj_offset> > 638f: 41 89 c5 mov %eax,%r13d > 6392: 4c 89 f0 mov %r14,%rax > 6395: 48 c1 e8 03 shr $0x3,%rax > 6399: 8a 04 18 mov (%rax,%rbx,1),%al > 639c: 84 c0 test %al,%al > 639e: 0f 85 f2 02 00 00...
2016 Jun 16
2
[PATCH v7 00/12] Support non-lru page migration
...lea 0x78(%r12),%r14 > 6384: 4c 89 ee mov %r13,%rsi > 6387: 4c 89 e7 mov %r12,%rdi > 638a: e8 86 c7 ff ff callq 2b15 <get_first_obj_offset> > 638f: 41 89 c5 mov %eax,%r13d > 6392: 4c 89 f0 mov %r14,%rax > 6395: 48 c1 e8 03 shr $0x3,%rax > 6399: 8a 04 18 mov (%rax,%rbx,1),%al > 639c: 84 c0 test %al,%al > 639e: 0f 85 f2 02 00 00...
2018 Feb 06
3
What does a dead register mean?
...le program I see the following sequence: ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx %r12 %r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d %r12w %r13w %r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def %rsp, implicit-def %ssp ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp RET 0 The ADJCALLSTACKDOWN64 has implicit-def dead %rsp. How...
2016 Jun 15
2
[PATCH v7 00/12] Support non-lru page migration
Hi Sergey, On Wed, Jun 15, 2016 at 04:59:09PM +0900, Sergey Senozhatsky wrote: > Hello Minchan, > > -next 4.7.0-rc3-next-20160614 > > > [ 315.146533] kasan: CONFIG_KASAN_INLINE enabled > [ 315.146538] kasan: GPF could be caused by NULL-ptr deref or user memory access > [ 315.146546] general protection fault: 0000 [#1] PREEMPT SMP KASAN > [ 315.146576] Modules
2016 Jun 15
2
[PATCH v7 00/12] Support non-lru page migration
Hi Sergey, On Wed, Jun 15, 2016 at 04:59:09PM +0900, Sergey Senozhatsky wrote: > Hello Minchan, > > -next 4.7.0-rc3-next-20160614 > > > [ 315.146533] kasan: CONFIG_KASAN_INLINE enabled > [ 315.146538] kasan: GPF could be caused by NULL-ptr deref or user memory access > [ 315.146546] general protection fault: 0000 [#1] PREEMPT SMP KASAN > [ 315.146576] Modules
2016 Jul 09
3
IPRA, interprocedural register allocation, question
...on Divisor using Euclid's Algorithm */ __asm__ __volatile__ ( "movl %1, %%r15d;" "movl %2, %%ecx;" "CONTD: cmpl $0, %%ecx;" "je DONE;" "xorl %%r13d, %%r13d;" "idivl %%ecx;" "movl %%ecx, %%r15d;" "movl %%r13d, %%ecx;" "jmp CONTD;" "DONE: movl %%r15d, %0;" : &quot...
2016 Jun 30
0
Help required regarding IPRA and Local Function optimization
...later sqlite3WhereBegin is optimized not to save callee saved registers this should obviously not happen. Here is assembly code that is printed with lldb dis command on run time failure and after careful observation I have identified one bug: ... 0x10002d8ff <+1855>: movl -0x74(%rbp), %r13d 0x10002d903 <+1859>: movq -0x30(%rbp), %r12 ; this contains address of a structure 0x10002d907 <+1863>: movq -0x38(%rbp), %r14 0x10002d90b <+1867>: movq -0x58(%rbp), %r15 0x10002d90f <+1871>: leaq -0x150(%rbp), %rdi 0x10002d916 <+1878>: mov...
2013 Sep 12
1
[LLVMdev] bug in X86 disasm code?
...\ ENTRY(EDX) \ ENTRY(EBX) \ ENTRY(sib) \ ENTRY(EBP) \ ENTRY(ESI) \ ENTRY(EDI) \ ENTRY(R8D) \ ENTRY(R9D) \ ENTRY(R10D) \ ENTRY(R11D) \ ENTRY(R12D) \ ENTRY(R13D) \ ENTRY(R14D) \ ENTRY(R15D) the ENTRY(sib) looks suspicious. that should be ENTRY(ESP), no? thanks. J -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130912/a2bd068c/attachment.htm...
2016 Jun 16
0
[PATCH v7 00/12] Support non-lru page migration
...4d 8d 74 24 78 lea 0x78(%r12),%r14 6384: 4c 89 ee mov %r13,%rsi 6387: 4c 89 e7 mov %r12,%rdi 638a: e8 86 c7 ff ff callq 2b15 <get_first_obj_offset> 638f: 41 89 c5 mov %eax,%r13d 6392: 4c 89 f0 mov %r14,%rax 6395: 48 c1 e8 03 shr $0x3,%rax 6399: 8a 04 18 mov (%rax,%rbx,1),%al 639c: 84 c0 test %al,%al 639e: 0f 85 f2 02 00 00 jne 6696 <zs_compac...
2016 Jul 12
2
IPRA, interprocedural register allocation, question
...on Divisor using Euclid's Algorithm */ __asm__ __volatile__ ( "movl %1, %%r15d;" "movl %2, %%ecx;" "CONTD: cmpl $0, %%ecx;" "je DONE;" "xorl %%r13d, %%r13d;" "idivl %%ecx;" "movl %%ecx, %%r15d;" "movl %%r13d, %%ecx;" "jmp CONTD;" "DONE: movl %%r15d, %0;" : &quot...
2016 Jun 30
4
Help required regarding IPRA and Local Function optimization
Hello Mentors, I am currently finding bug in Local Function related optimization due to which runtime failures are observed in some test cases, as those test cases are containing very large function with recursion and object oriented code so I am not able to find a pattern which is causing failure. So I tried following simple case to understand expected behavior from this optimization. Consider
2016 Jun 25
3
Tail call optimization is getting affected due to local function related optimization with IPRA
...maks collected by RegUsageInfoCollector pass. Function Name : bitrv2 Clobbered Registers: AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI ESP RAX RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B R9B R10B R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W R10W R11W R12W R13W R14W R15W How ever caller of bitrv2, makewt has callee saved registers as per CC, but this code results in segmentation fault when compliled with O1 because makewt has value of *ip in R14 register and that is stored and restore by makewt at begining of call bu...