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...hose four registers because they are still useful with some *_NOREX instructions. It looks like this: def GR8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> { let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ static const unsigned X86_GR8_AO_64[] = { X86::AL, X86::CL, X86::DL, X86::SI...

..._subreg_32bit : PatLeaf<(i32 3)>; > > def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, > R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], > [AL, CL, DL, BL, SPL, BPL, SIL, DIL, > R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; > > I admit the way it's specified is not very elegant. We'll clean it up > some day. > > Evan > Even in that case you can not have a 0 as a SubIdx. e.g. the code below won't work def x86_subreg_8bit : PatLeaf<(i32 0)>; def : SubRe...

...fter reg alloc on a simple program I see the following sequence: ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx %r12 %r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d %r12w %r13w %r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def %rsp, implicit-def %ssp ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp RET 0 The ADJCALLSTACKDOWN64 has imp...

...: PatLeaf<(i32 3)>; >> >> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, >> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], >> [AL, CL, DL, BL, SPL, BPL, SIL, DIL, >> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; >> >> I admit the way it's specified is not very elegant. We'll clean it up >> some day. >> >> Evan >> > Even in that case you can not have a 0 as a SubIdx. > e.g. the code below won't work > > def x86_subreg_8bit : P...

...f<(i32 2)>; def x86_subreg_32bit : PatLeaf<(i32 3)>; def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], [AL, CL, DL, BL, SPL, BPL, SIL, DIL, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; I admit the way it's specified is not very elegant. We'll clean it up some day. Evan On Oct 13, 2008, at 11:24 AM, sanjiv gupta wrote: > On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote: >> >> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.c...

On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote: > > On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > > > What’s the value produced by an INSERT_SUBREG node? Is it a chain? > > > No, insert_subreg returns a value: > > > v1 = insert_subreg v2, v3, idx > > > v1 and v2 will have the same type, e.g. i16, and v3 must have a >

...s set of collbered register as per regmaks collected by RegUsageInfoCollector pass. Function Name : bitrv2 Clobbered Registers: AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI ESP RAX RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B R9B R10B R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W R10W R11W R12W R13W R14W R15W How ever caller of bitrv2, makewt has callee saved registers as per CC, but this code results in segmentation fault when compliled with O1 because makewt has value of *ip in R14 register and that is stored and re...

...m I see the > following sequence: > > ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead > %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp > CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx > %r12 %r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d > %r12w %r13w %r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def > %rsp, implicit-def %ssp > ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead > %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp > RET 0 >...

...er the call, "val" (i.e., storage location rbp - 0x8) is used in the addition to calculate the returned value. However, when I print the RegMask operand for the call machine instruction, I get the following: <regmask %BH %BL %BP %BPL %BX %EBP %EBX %RBP %RBX %R12 %R13 %R14 %R15 %R12B %R13B %R14B %R15B %R12D %R13D %R14D %R15D %R12W %R13W %R14W %R15W> I don't see xmm1 as being preserved across this call. Am I missing something? Thanks for your help! On Wed, Jun 22, 2016 at 5:01 PM, Sanjoy Das <sanjoy at playingwithpointers.com> wrote: > Hi Rob, > > Rob Lyerly...

...aks collected by RegUsageInfoCollector pass. > > Function Name : bitrv2 > Clobbered Registers: > AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI > ESP RAX > RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B > R9B R10B > R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W > R10W R11W > R12W R13W R14W R15W > > How ever caller of bitrv2, makewt has callee saved registers as per CC, > but this > code results in segmentation fault when compliled with O1 because makewt > has value > of *ip in...

> The main advantage of the clang-built Android ARM(32-bit) hammerhead kernel for my Nexus 5 has been the better battery usage when compared to that of gcc-built kernel, with the same kernel config and hardware(my Nexus 5 Android Smartphone). Details of the same can be found below. To be fair, the GCC version which comes with the android ndk has not been updated for four years, while the clang

...lector pass. >> >> Function Name : bitrv2 >> Clobbered Registers: >> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI >> ESP RAX >> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B >> R9B R10B >> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W >> R10W R11W >> R12W R13W R14W R15W >> >> How ever caller of bitrv2, makewt has callee saved registers as per CC, >> but this >> code results in segmentation fault when compliled with O1 because makewt >&...

I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined

...per regmaks collected by RegUsageInfoCollector pass. > > Function Name : bitrv2 > Clobbered Registers: > AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI ESP RAX > RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B R9B R10B > R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W R10W R11W > R12W R13W R14W R15W > > How ever caller of bitrv2, makewt has callee saved registers as per CC, but this > code results in segmentation fault when compliled with O1 because makewt has value > of *ip in R14 register...

...t;> Function Name : bitrv2 >>> Clobbered Registers: >>> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI >>> ESP RAX >>> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B >>> R9B R10B >>> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W >>> R10W R11W >>> R12W R13W R14W R15W >>> >>> How ever caller of bitrv2, makewt has callee saved registers as per CC, >>> but this >>> code results in segmentation fault when compliled with...

...> >> > >> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, > >> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], > >> [AL, CL, DL, BL, SPL, BPL, SIL, DIL, > >> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; > >> > >> I admit the way it's specified is not very elegant. We'll clean it up > >> some day. > >> > >> Evan > >> > > Even in that case you can not have a 0 as a SubIdx. > > e.g. the code below won't wo...

...itrv2 >>>> Clobbered Registers: >>>> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI >>>> ESP RAX >>>> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B >>>> R9B R10B >>>> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W >>>> R10W R11W >>>> R12W R13W R14W R15W >>>> >>>> How ever caller of bitrv2, makewt has callee saved registers as per CC, >>>> but this >>>> code results in segmentation f...

Hi Rob, Rob Lyerly via llvm-dev wrote: > I'm looking for a way to get all the caller-saved registers (both the > register and the stack slot at which it was saved) for a given function > call site in the backend. What's the best way to grab this > information? Is it possible to get this information if I have the > MachineInstr of the function call? I'm currently

Hi everyone, I'm looking for a way to get all the caller-saved registers (both the register and the stack slot at which it was saved) for a given function call site in the backend. What's the best way to grab this information? Is it possible to get this information if I have the MachineInstr of the function call? I'm currently targeting the AArch64 & X86 backends. Thanks! --