Displaying 4 results from an estimated 4 matches for "r135462".
2011 Jul 19
0
[LLVMdev] Custom lowering of load with extension
...cause
> isLoadExtLegal returns true in the case of custom lowering of load which
> does not seem logical to me (do you have an explanation for this ?).
>
> Well, I assume I didn't do sth the right way... Can you point a mistake in
> my reasoning ?
Looks like a bug to me too. :) r135462 should fix it.
-Eli
2011 Jul 19
2
[LLVMdev] Custom lowering of load with extension
Hi,
The target I am working on does not support i8 loading: it supports only 32
bit aligned loads.
I had to custom lower i8 load so that only i32 loads are generated.
My issue is the following:
In a very specific case, the lowering stage generates the following pattern
where the load is a i32 load:
(and (load x), 255)
This pattern is somehow converted by the DAG combiner back to:
(zextload x,
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
On Wed, Jul 27, 2011 at 3:50 PM, Matt Johnson
<johnso87 at crhc.illinois.edu> wrote:
> Hi Eli,
>
> On 07/27/2011 04:59 PM, Eli Friedman wrote:
>>
>> On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson
>> <johnso87 at crhc.illinois.edu> wrote:
>>>
>>> Hi All,
>>> I'm writing a backend for a target which only supports 4-byte,
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
Hi Eli,
On 07/27/2011 04:59 PM, Eli Friedman wrote:
> On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson
> <johnso87 at crhc.illinois.edu> wrote:
>> Hi All,
>> I'm writing a backend for a target which only supports 4-byte,
>> 4-byte-aligned loads and stores. I custom-lower all {*EXT}LOAD and
>> STORE nodes in TargetISelLowering.cpp to take advantage of