search for: r127

Author: ultrotter Date: 2006-03-21 16:54:07 +0000 (Tue, 21 Mar 2006) New Revision: 127 Modified: trunk/xen-3.0/debian/xen-utils-3.0.postrm Log: Stop xend & xendomains on remove, and call update-rc.d on purge... Modified: trunk/xen-3.0/debian/xen-utils-3.0.postrm =================================================================== --- trunk/xen-3.0/debian/xen-utils-3.0.postrm 2006-03-21

...ibtextcat.so.0 > > > > These would both seem to be related to plugins, and don't seem to be > > required as package dependencies by the RPM from what I can see from the > > SRPM. > > > > Anyone know what packages I need to satisfy these dependencies? > lz4-r127-1.el6.i686 and libtextcat-2.2-10.el6.i686 >From what source? I don't see them in any of the normal RHEL channels or in EPEL. I also don't see them in the Dovecot repo (or, unless I'm missing something, in the specfile's install requires). (BTW, I'm on x86_64 arch, but shoul...

...pecific reason for not doing like this? I am not sure whether I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case, may be something like I only need to define r0~r127 as register for i32 register (each r# is just enough for simd8 i32). Then the register allocator never need to go to allocate the sub-registers, just operate them as a whole. right? Yes, it looks really easy for divergent registers. But I think then I would lose the ability to allocate uniform reg...

...nd target for Intel GPU. I would start from targeting OpenCL language first. But I am not quite familiar with LLVM backend infrastructure. I have some problem on describing the RegisterInfo. Intel GPU launches lots of hardware threads to do GPGPU workload. Each hardware thread has 128 registers(r0-r127), with each one of size 32 byte. Each hardware thread may run in SIMD 8/16/32 way, which maps to 8/16/32 OpenCL working items. And the SIMD width is chosen at compile time (normally chosen according to register pressure, bigger simd width means bigger register pressure). Note each instruction has e...

I've been trying to upgrade Dovecot-ee package (on EL6/x86_64) from 2.2.15.8-1 to 2.2.16.2-1. It's complaining on these two dependencies: liblz4.so.1 libtextcat.so.0 These would both seem to be related to plugins, and don't seem to be required as package dependencies by the RPM from what I can see from the SRPM. Anyone know what packages I need to satisfy these dependencies?

...R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176,...

Hi Micah, > In X86InstrInfo.td for Call Instructions, it mentions that Uses for > argument registers are added manually. Can someone point me to the > location where they are added as the comment doesn't reference a > where or how? the register uses are added by the function X86TargetLowering::LowerCall() during the DAG Lowering phase. This is the relevant code segment: // Add

...ies: > > liblz4.so.1 > libtextcat.so.0 > > These would both seem to be related to plugins, and don't seem to be > required as package dependencies by the RPM from what I can see from the > SRPM. > > Anyone know what packages I need to satisfy these dependencies? lz4-r127-1.el6.i686 and libtextcat-2.2-10.el6.i686 Eric

...like this? > I am not sure whether I understand your point correctly. For "just model > one thread", > do you mean "only considering ONE of the 8/16 working lanes that running > in lock-step way"?? > > For my case, may be something like I only need to define r0~r127 as > register for i32 register (each r# is just enough for simd8 i32). > Then the register allocator never need to go to allocate the > sub-registers, just operate them as a whole. right? > > Yes, it looks really easy for divergent registers. But I think then I > would lose the ab...

...39;' " + "AND taggings.tag_id = tags.id AND tags.name IN (?)", list] ) end Originally, this built a string directly to pass to find_by_sql, but I changed it thusly: trunk/vendor/plugins/acts_as_taggable/lib/acts_as_taggable.rb r13 r127 25 25 module SingletonMethods 26 26 def find_tagged_with(list) 27 find_by_sql( 28 "SELECT #{table_name}.* FROM #{table_name}, tags, taggings " + 29 "WHERE #{table_name}.#{primary_key} = taggings.taggable_id " + 30 "A...