Displaying 15 results from an estimated 15 matches for "r10b".
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r10
2011 Jun 15
0
[LLVMdev] Custom allocation orders
...We don't want to reserve those four registers because they are still useful with some *_NOREX instructions.
It looks like this:
def GR8 : RegisterClass<"X86", [i8], 8,
[AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
static const unsigned X86_GR8_AO_64[] = {
X86::AL,...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...>;
> def x86_subreg_32bit : PatLeaf<(i32 3)>;
>
> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
>
> I admit the way it's specified is not very elegant. We'll clean it up
> some day.
>
> Evan
>
Even in that case you can not have a 0 as a SubIdx.
e.g. the code below won't work
def x86_subreg_8bit : PatLeaf<(i32 0)&g...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...86_subreg_32bit : PatLeaf<(i32 3)>;
>>
>> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
>> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
>> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
>> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
>>
>> I admit the way it's specified is not very elegant. We'll clean it up
>> some day.
>>
>> Evan
>>
> Even in that case you can not have a 0 as a SubIdx.
> e.g. the code below won't work
>
> def x86_...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...g_16bit : PatLeaf<(i32 2)>;
def x86_subreg_32bit : PatLeaf<(i32 3)>;
def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
I admit the way it's specified is not very elegant. We'll clean it up
some day.
Evan
On Oct 13, 2008, at 11:24 AM, sanjiv gupta wrote:
> On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote:
>>
>> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gu...
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote:
>
> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
>
> > What’s the value produced by an INSERT_SUBREG node? Is it a chain?
>
>
> No, insert_subreg returns a value:
>
>
> v1 = insert_subreg v2, v3, idx
>
>
> v1 and v2 will have the same type, e.g. i16, and v3 must have a
>
2016 Jun 25
3
Tail call optimization is getting affected due to local function related optimization with IPRA
...ion following is set of collbered
register as
per regmaks collected by RegUsageInfoCollector pass.
Function Name : bitrv2
Clobbered Registers:
AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI ESP
RAX
RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B R9B
R10B
R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W R10W
R11W
R12W R13W R14W R15W
How ever caller of bitrv2, makewt has callee saved registers as per CC, but
this
code results in segmentation fault when compliled with O1 because makewt
has value
of *ip in R14 register and that i...
2016 Jun 25
0
Tail call optimization is getting affected due to local function related optimization with IPRA
...ter as
> per regmaks collected by RegUsageInfoCollector pass.
>
> Function Name : bitrv2
> Clobbered Registers:
> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI
> ESP RAX
> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B
> R9B R10B
> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W
> R10W R11W
> R12W R13W R14W R15W
>
> How ever caller of bitrv2, makewt has callee saved registers as per CC,
> but this
> code results in segmentation fault when compliled with O1 because makewt
> has...
2016 Jun 26
3
Tail call optimization is getting affected due to local function related optimization with IPRA
...ected by RegUsageInfoCollector pass.
>>
>> Function Name : bitrv2
>> Clobbered Registers:
>> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI
>> ESP RAX
>> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B
>> R9B R10B
>> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W
>> R10W R11W
>> R12W R13W R14W R15W
>>
>> How ever caller of bitrv2, makewt has callee saved registers as per CC,
>> but this
>> code results in segmentation fault when compliled with...
2016 Jun 28
2
Tail call optimization is getting affected due to local function related optimization with IPRA
...red register as
> per regmaks collected by RegUsageInfoCollector pass.
>
> Function Name : bitrv2
> Clobbered Registers:
> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI ESP RAX
> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B R9B R10B
> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W R10W R11W
> R12W R13W R14W R15W
>
> How ever caller of bitrv2, makewt has callee saved registers as per CC, but this
> code results in segmentation fault when compliled with O1 because makewt has value
> of...
2016 Jun 27
0
Tail call optimization is getting affected due to local function related optimization with IPRA
...or pass.
>>>
>>> Function Name : bitrv2
>>> Clobbered Registers:
>>> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI
>>> ESP RAX
>>> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B
>>> R9B R10B
>>> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W
>>> R10W R11W
>>> R12W R13W R14W R15W
>>>
>>> How ever caller of bitrv2, makewt has callee saved registers as per CC,
>>> but this
>>> code results in segmentati...
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...af<(i32 3)>;
> >>
> >> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
> >> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> >> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> >> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
> >>
> >> I admit the way it's specified is not very elegant. We'll clean it up
> >> some day.
> >>
> >> Evan
> >>
> > Even in that case you can not have a 0 as a SubIdx.
> > e.g. the code...
2016 Jun 28
0
Tail call optimization is getting affected due to local function related optimization with IPRA
...t;>>> Function Name : bitrv2
>>>> Clobbered Registers:
>>>> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI
>>>> ESP RAX
>>>> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B
>>>> R9B R10B
>>>> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W
>>>> R10W R11W
>>>> R12W R13W R14W R15W
>>>>
>>>> How ever caller of bitrv2, makewt has callee saved registers as per CC,
>>>> but this
>>>>...
2016 Jun 28
2
Tail call optimization is getting affected due to local function related optimization with IPRA
...>>>>>> Function Name : bitrv2
>>>>>> Clobbered Registers:
>>>>>> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI ESP RAX
>>>>>> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B R9B R10B
>>>>>> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W R10W R11W
>>>>>> R12W R13W R14W R15W
>>>>>>
>>>>>> How ever caller of bitrv2, makewt has callee saved registers as per CC, but this
>>>>...
2008 Apr 16
0
[LLVMdev] Being able to know the jitted code-size before emitting
...R10D: case X86::R11D:
> - case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
> - case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
> - case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
> - case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
> - case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
> - case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
> - case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
> - return true;
> - }
> - return false;...
2008 Apr 15
4
[LLVMdev] Being able to know the jitted code-size before emitting
OK, here's a new patch that adds the infrastructure and the
implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize.
Both functions are virtual functions defined in TargetInstrInfo.h.
For X86, I moved some commodity functions from X86CodeEmitter to
X86InstrInfo.
What do you think?
Nicolas
Evan Cheng wrote:
>
> I think both of these belong to TargetInstrInfo. And