search for: r1025

a really good idea Charles ;-) 2007/7/11, Charles Lepple <clepple-guest at alioth.debian.org>: > Author: clepple-guest > Date: Wed Jul 11 03:20:44 2007 > New Revision: 1025 > > Log: > Added bash completion script for 'upsc'. > ... you should also consider adding a Makefile + configure test for auto installation (based upon the existence of

...ng a language that uses virtual registers and not physical registers. So the easiest way to implement this is to use virtual registers, except that they are being restarted after each function and clobbering registers in previous functions. For example: start function 0 r1024 = mov %var0.0 r1025 = mov %var0.1 lots of intermediate code call function1 w/ 3 parameters more intermediate code %r1300 = add %call.result, %r1024 end function 0 start function 1 %r1024 = mov %var1.0 %r1025 = mov %var1.1 %r1026 = mov %var1.2 some code return some value end function 0 The mov to r10...

No, there isn't something like that right now. What are you trying to accomplish? If you wish to implement this, it shouldn't be hard to do. Right now, MachineRegisterInfo re-starts virtual register number at TargetRegisterInfo::FirstVirtualRegister. You can add a mechanism to change that to a variable instead. Evan On Oct 20, 2008, at 1:43 PM, Villmow, Micah wrote: > Is

Is there currently a way to have virtual register allocation information be saved across functions so that if I create a new virtual register in a function that it doesn't use a virtual register allocated in any previous function? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054

...is the sample code: void myFunction( int* src, int* dst, int i ) { dst[i] = src[i]; i = i + 4; return; } I want to get this translate to my machine code as following: shl R1028, R1026, 2 add_pointer R1029, R1024, R1028 // incrementing the src pointer load R1030, R1029 add_pointer R1031, R1025,R1028 // calculating the dst address store R1030, R1031 mov R1031, 4 add R1032, R1026, R1031 //scalar addition ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>; def P32RC : RegisterCl...

...... DL = ADDi8 CL, 42 In your case, you'd define your vector register class with 4 subregs, one for each piece. Unfortunately, none of this exists yet :(. To handle truncates and extends on X86, we currently emulate this by generating machineinstrs like: r1024 = X86_LOADi16 ... r1025 = TRUNCATE_i16_to_i8 r1024 r1026 = ADDi8 r1025, 42 In the asmprinter, we print TRUNCATE_i16_to_i8 as a commented out noop if the register allocator happens to allocate 1024 and 1025 to the same register. If not, it uses an asmprinter hack to print this as a copy instruction. This is horrib...

...#39;ve looked into this more and there is a part where I'm working with physical registers. If there is a function call, there is a copy from virtual register space to the functions that are expected to be passed into the register. So it looks something like this: ... do some work ... Mov %r0, %r1025 Mov %r1, %r1026 Mov %r2, %r1027 Call someFunc %r0, %r1, %r2 <-- this func stores to memory Ret The moves to the physical registers are being deleted as NonAllocatableRegs is set to all one's and then inverted, and since these are deleted, every instruction that they depended on is also dele...

On Apr 23, 2007, at 1:43 PM, Christopher Lamb wrote: > On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote: > >> On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: >> >>> On Mon, 23 Apr 2007, Christopher Lamb wrote: >>>> How can one let the back end know how to insert and extract >>>> elements of >>>> a vector through sub-register

...is the sample code: void myFunction( int* src, int* dst, int i ) { dst[i] = src[i]; i = i + 4; return; } I want to get this translate to my machine code as following: shl R1028, R1026, 2 add_pointer R1029, R1024, R1028 // incrementing the src pointer load R1030, R1029 add_pointer R1031, R1025,R1028 // calculating the dst address store R1030, R1031 mov R1031, 4 add R1032, R1026, R1031 //scalar addition ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>; def P32RC : RegisterCl...

...#39;ve looked into this more and there is a part where I'm working with physical registers. If there is a function call, there is a copy from virtual register space to the functions that are expected to be passed into the register. So it looks something like this: ... do some work ... Mov %r0, %r1025 Mov %r1, %r1026 Mov %r2, %r1027 Call someFunc %r0, %r1, %r2 <-- this func stores to memory Ret The moves to the physical registers are being deleted as NonAllocatableRegs is set to all one's and then inverted, and since these are deleted, every instruction that they depended on is also dele...

On Apr 14, 2010, at 1:55 PMPDT, Villmow, Micah wrote: > I’ve recently sync’d to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc

I've recently sync'd to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc with my backend. Before entering this pass, everything