search for: r1024

I'm targeting a language that uses virtual registers and not physical registers. So the easiest way to implement this is to use virtual registers, except that they are being restarted after each function and clobbering registers in previous functions. For example: start function 0 r1024 = mov %var0.0 r1025 = mov %var0.1 lots of intermediate code call function1 w/ 3 parameters more intermediate code %r1300 = add %call.result, %r1024 end function 0 start function 1 %r1024 = mov %var1.0 %r1025 = mov %var1.1 %r1026 = mov %var1.2 some code return some value end function...

...6. In particular, an integer truncate or an extend (e.g. i16 -> i8) wants to make use of subregisters. Consider code like this: t1 = load i16 t2 = truncate i16 t1 to i8 t3 = add i8 t2, 42 What we would really want to generate is something like this at the machine instr level: r1024 = X86_LOADi16 ... ;; r1024 is i16 r1026 = ADDi8 r1024[subreg #0], 42 More specifically, we want to be able to define, for each register class, a set of subregister classes. In the X86 world, the 64-bit register classes could have subregclass0 = i8 parts, subregclass1 = i16 parts, subreg...

On Apr 23, 2007, at 1:43 PM, Christopher Lamb wrote: > On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote: > >> On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: >> >>> On Mon, 23 Apr 2007, Christopher Lamb wrote: >>>> How can one let the back end know how to insert and extract >>>> elements of >>>> a vector through sub-register

No, there isn't something like that right now. What are you trying to accomplish? If you wish to implement this, it shouldn't be hard to do. Right now, MachineRegisterInfo re-starts virtual register number at TargetRegisterInfo::FirstVirtualRegister. You can add a mechanism to change that to a variable instead. Evan On Oct 20, 2008, at 1:43 PM, Villmow, Micah wrote: > Is

Is there currently a way to have virtual register allocation information be saved across functions so that if I create a new virtual register in a function that it doesn't use a virtual register allocated in any previous function? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054

...e member functions > divide pretty cleanly between than and LiveIntervals. Beyond that, one of the issues is the "r2rmap" and "rep" function. As you've noticed, the coallescer basically uses these to avoid rewriting the code after it does coallescing. For example, if r1024 is coallesced with r1026, it leaves all uses of both registers in the code, instead of rewriting uses of r1026 with r1024 and deleting all memory of r1026. This mades sense long ago, but now it is increasingly clear that this is a bad idea. I would much rather have the coallescer be responsibl...

...e references to papers that talk about the various algorithms? > Beyond that, one of the issues is the "r2rmap" and "rep" function. As > you've noticed, the coallescer basically uses these to avoid rewriting the > code after it does coallescing. For example, if r1024 is coallesced with > r1026, it leaves all uses of both registers in the code, instead of > rewriting uses of r1026 with r1024 and deleting all memory of r1026. This > mades sense long ago, but now it is increasingly clear that this is a bad > idea. I would much rather have the coal...

On Mon, Oct 20, 2008 at 2:14 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > The mov to r1024 in function 1 clobbers the data from function 0. The only > ways I can think to get around this, is to push every virtual register used > in a function to a stack or some internal data structure and then pull them > back out for each function call. Just to double-check, are you planning o...

Hi, I am starting to learn using libvirt with kvm on CentOS 6. Just used this command to start a guest: virt-install -ntest -r1024 --vcpus=1 -c/var/lib/libvirt/images/CentOS-6.0-x86_64-netinstall.iso --os-type=linux --os-variant=rhel6 --disk vol=kvmguests/test --vnc -v --virt-type=kvm --check-cpu --prompt --arch=x86_64 Then I found out that I misconfigured vnc. And I do not know how to gracefully stop qemu. So I killed it....

Hi all, As I work toward improving LLVM register allocation, I've come across the need to do some refactoring. Specifically, I would like to separate register coalescing from live interval analysis. Right now LiveIntervals handles both. The reason I want to separate them is that other types of register allocators might like to do coalescing differently (e.g. graph coloring does it by

On Thu, 12 Apr 2007, David Greene wrote: >> Beyond that, one of the issues is the "r2rmap" and "rep" function. As >> you've noticed, the coallescer basically uses these to avoid rewriting the >> code after it does coallescing. For example, if r1024 is coallesced with >> r1026, it leaves all uses of both registers in the code, instead of >> rewriting uses of r1026 with r1024 and deleting all memory of r1026. This >> mades sense long ago, but now it is increasingly clear that this is a bad >> idea. I would much rather h...

...to do some refactoring. Yay! >> Beyond that, one of the issues is the "r2rmap" and "rep" >> function. As >> you've noticed, the coallescer basically uses these to avoid >> rewriting the >> code after it does coallescing. For example, if r1024 is >> coallesced with >> r1026, it leaves all uses of both registers in the code, instead of >> rewriting uses of r1026 with r1024 and deleting all memory of >> r1026. This >> mades sense long ago, but now it is increasingly clear that this >> is a bad >...

...e mapping LLVM add to my machine add instruction based on the oprand types. Here is the sample code: void myFunction( int* src, int* dst, int i ) { dst[i] = src[i]; i = i + 4; return; } I want to get this translate to my machine code as following: shl R1028, R1026, 2 add_pointer R1029, R1024, R1028 // incrementing the src pointer load R1030, R1029 add_pointer R1031, R1025,R1028 // calculating the dst address store R1030, R1031 mov R1031, 4 add R1032, R1026, R1031 //scalar addition ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : Regis...

...e mapping LLVM add to my machine add instruction based on the oprand types. Here is the sample code: void myFunction( int* src, int* dst, int i ) { dst[i] = src[i]; i = i + 4; return; } I want to get this translate to my machine code as following: shl R1028, R1026, 2 add_pointer R1029, R1024, R1028 // incrementing the src pointer load R1030, R1029 add_pointer R1031, R1025,R1028 // calculating the dst address store R1030, R1031 mov R1031, 4 add R1032, R1026, R1031 //scalar addition ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : Regis...