Displaying 4 results from an estimated 4 matches for "r100760".
2016 Sep 21
8
[PATCH 0/5] GPU-DRM-nouveau: Fine-tuning for five function implementations
From: Markus Elfring <elfring at users.sourceforge.net>
Date: Wed, 21 Sep 2016 09:09:09 +0200
A few update suggestions were taken into account
from static source code analysis.
Markus Elfring (5):
Use kmalloc_array() in nvbios_iccsense_parse()
Use kmalloc_array() in gt215_link_train()
Delete unnecessary braces
Adjust a kzalloc() call in gt215_ram_new()
Add space after an
2016 Sep 21
0
[PATCH 3/5] GPU-DRM-nouveau: Delete unnecessary braces
.../
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
if (bins[i] > qty) {
bin = i + 3;
qty = bins[i];
}
- }
train->r_100720 = 0;
for (i = 0; i < 8; i++) {
@@ -729,9 +728,8 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq)
ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
}
- if (device->chipset == 0xa3 && freq > 500000) {
+ if (device->chipset == 0xa3 && freq > 500000)
ram_mask(fuc, 0x100700, 0x00000006, 0x00000000);
- }
/* Final switch */
if (mclk.pll) {
@@ -745,12 +743,11 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq...
2014 Sep 29
18
Implement reclocking for DDR2, DDR3, GDDR3
Following a series of patches that implement memory reclocking for NVA3/5/8 with
DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics
cards, but I expect reclocking now to work on many more.
Testers can pick up these patches and test it by enabling pstate
(nouveau.pstate=1). They should then be able to change clocks by writing to
/sys/class/drm/card0/device/pstate. Correct
2014 Sep 12
6
NVA3: Small misc mem reclocking fixes
Patch 1 fixes nva3 bailing due to not finding the right ramcfg
Patch 2 is a resend rebased on 3.17.0-rc4 for setting the vblank period
Patch 3-5 handle writes to per-partition registers, for which NVA3 does not
have special broadcast regs available.
Patch 6 removes local structs from NVA3 reclocking in favour of the already
existing "ram->base." variables, like in NVE0
As always,