Displaying 3 results from an estimated 3 matches for "r0_z".
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r0_1
2005 May 06
3
[LLVMdev] avoid live range overlap of "vector" registers
...void the
code generator overlaps the live ranges of vector registers?
i could define a 'definition' for each scalar register, but it's tedious:
class FooReg<string n> : Register<n> {}
def r0_x: FooReg<"r0.x">;
def r0_y: FooReg<"r0.y">;
def r0_z: FooReg<"r0.z">;
def r0_w: FooReg<"r0.w">;
def r1_x: FooReg<"r1.x">;
def r1_y: FooReg<"r1.y">;
def r1_z: FooReg<"r1.z">;
def r1_w: FooReg<"r1.w">;
...
and there are 32 vector registers!
i've read...
2005 Apr 20
1
[LLVMdev] adding new instructions to support "swizzle" and "writemask"
...ts swizzle
and writemask.
I have a few solutions:
(1) Treat each channel of a register as a individual SSA variable.
This could generate inefficient machine code.
For example, the instruction:
add r0.xz, r1.y, r2.wx
is translated to two LLVM instructions:
r0_x = add float r1_y, r2_w
r0_z = add float r1_y, r2_x
Subsequent optimization passes could insert other instructions between
these two instruction (for example, in instruction scheduling pass). I
don't know how they could be easily merged back into one instruction.
It could lead to inefficient machine code (though correct...
2005 May 10
0
[LLVMdev] avoid live range overlap of "vector" registers
...is precedent for this...
-Chris
> i could define a 'definition' for each scalar register, but it's tedious:
>
>
> class FooReg<string n> : Register<n> {}
>
> def r0_x: FooReg<"r0.x">;
> def r0_y: FooReg<"r0.y">;
> def r0_z: FooReg<"r0.z">;
> def r0_w: FooReg<"r0.w">;
> def r1_x: FooReg<"r1.x">;
> def r1_y: FooReg<"r1.y">;
> def r1_z: FooReg<"r1.z">;
> def r1_w: FooReg<"r1.w">;
> ...
>
> and there ar...