Displaying 3 results from an estimated 3 matches for "r0_x".
Did you mean:
c0_x
2005 May 06
3
[LLVMdev] avoid live range overlap of "vector" registers
...xyzw, r1.xzyw, r2.xyzw
My question is how to define the register in .td file to avoid the
code generator overlaps the live ranges of vector registers?
i could define a 'definition' for each scalar register, but it's tedious:
class FooReg<string n> : Register<n> {}
def r0_x: FooReg<"r0.x">;
def r0_y: FooReg<"r0.y">;
def r0_z: FooReg<"r0.z">;
def r0_w: FooReg<"r0.w">;
def r1_x: FooReg<"r1.x">;
def r1_y: FooReg<"r1.y">;
def r1_z: FooReg<"r1.z">;
def r1_w: FooR...
2005 Apr 20
1
[LLVMdev] adding new instructions to support "swizzle" and "writemask"
...n or intrinsic function supports swizzle
and writemask.
I have a few solutions:
(1) Treat each channel of a register as a individual SSA variable.
This could generate inefficient machine code.
For example, the instruction:
add r0.xz, r1.y, r2.wx
is translated to two LLVM instructions:
r0_x = add float r1_y, r2_w
r0_z = add float r1_y, r2_x
Subsequent optimization passes could insert other instructions between
these two instruction (for example, in instruction scheduling pass). I
don't know how they could be easily merged back into one instruction.
It could lead to inefficien...
2005 May 10
0
[LLVMdev] avoid live range overlap of "vector" registers
...g the
tedious thing and including them all. The IA64 backend has 3*128
registers, so there is precedent for this...
-Chris
> i could define a 'definition' for each scalar register, but it's tedious:
>
>
> class FooReg<string n> : Register<n> {}
>
> def r0_x: FooReg<"r0.x">;
> def r0_y: FooReg<"r0.y">;
> def r0_z: FooReg<"r0.z">;
> def r0_w: FooReg<"r0.w">;
> def r1_x: FooReg<"r1.x">;
> def r1_y: FooReg<"r1.y">;
> def r1_z: FooReg<"...