search for: quickpath

...crux of my comments - just change > > the slowpath to complex name at that point to better reflect what > > it does. > > Actually in my v11 patch, I subdivided the slowpath into a slowpath for > the pending code and slowerpath for actual queuing. Perhaps, we could > use quickpath and slowpath instead. Anyway, it is a minor detail that we > can discuss after the core code get merged. > > -Longman Why not do it the right way the first time around? That aside - these optimization - seem to make the code harder to read. And they do remind me of the scheduler code in...

...crux of my comments - just change > > the slowpath to complex name at that point to better reflect what > > it does. > > Actually in my v11 patch, I subdivided the slowpath into a slowpath for > the pending code and slowerpath for actual queuing. Perhaps, we could > use quickpath and slowpath instead. Anyway, it is a minor detail that we > can discuss after the core code get merged. > > -Longman Why not do it the right way the first time around? That aside - these optimization - seem to make the code harder to read. And they do remind me of the scheduler code in...

...IA Technologies, Inc. USB 2.0 (rev 63) 04:0c.3 FireWire (IEEE 1394): VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller (rev 46) 04:0e.0 Mass storage controller: Promise Technology, Inc. PDC40775 (SATA 300 TX2plus) (rev 02) ff:00.0 Host bridge: Intel Corporation Core Processor QuickPath Architecture Generic Non-Core Registers (rev 04) ff:00.1 Host bridge: Intel Corporation Core Processor QuickPath Architecture System Address Decoder (rev 04) ff:02.0 Host bridge: Intel Corporation Core Processor QPI Link 0 (rev 04) ff:02.1 Host bridge: Intel Corporation Core Processor QPI Physical...

....1 Ethernet controller [0200]: Intel Corporation 82576 Gigabit Network Connection [8086:10c9] (rev 01) 09:00.0 VGA compatible controller [0300]: Matrox Electronics Systems Ltd. MGA G200e [Pilot] ServerEngines (SEP1) [102b:0522] (rev 02) ff:00.0 Host bridge [0600]: Intel Corporation Xeon 5600 Series QuickPath Architecture Generic Non-core Registers [8086:2c70] (rev 02) ff:00.1 Host bridge [0600]: Intel Corporation Xeon 5600 Series QuickPath Architecture System Address Decoder [8086:2d81] (rev 02) ff:02.0 Host bridge [0600]: Intel Corporation Xeon 5600 Series QPI Link 0 [8086:2d90] (rev 02) ff:02.1 Host...

On 7/28/2016 3:41 PM, Fawzy Ibrahim wrote: > LSI SATA MEGARAID 95Q9 afaik, the megaraid cards are mostly all SAS, which support SATA drives, except very old ones were SCSI. Ok, I do see they had a series of MegaRAID SATA 150-xx and 300-xx cards, these were 64 bit PCI or PCI-X cards. 95Q9 does not appear to be a valid card number, 9240, 9260, 9280 are some pci-express SAS MegaRaid

...t controller [0200]: Intel Corporation 82576 Gigabit Network Connection [8086:10c9] (rev 01) > 09:00.0 VGA compatible controller [0300]: Matrox Electronics Systems Ltd. MGA G200e [Pilot] ServerEngines (SEP1) [102b:0522] (rev 02) > ff:00.0 Host bridge [0600]: Intel Corporation Xeon 5600 Series QuickPath Architecture Generic Non-core Registers [8086:2c70] (rev 02) > ff:00.1 Host bridge [0600]: Intel Corporation Xeon 5600 Series QuickPath Architecture System Address Decoder [8086:2d81] (rev 02) > ff:02.0 Host bridge [0600]: Intel Corporation Xeon 5600 Series QPI Link 0 [8086:2d90] (rev 02) &gt...

Anyone can help me with this problem I''ve described here: https://bugzilla.novell.com/show_bug.cgi?id=612006 I''ve had XEN4.0 working on CentOS 5.4 platform without these problems.  I''m trying to do the same now with a newer laptop and CentOS didn''t recognise half hte drivers.  The latest opensuse 11.3 does have these drivers and specifically nouveau

...01) 48:03.2 SD Host controller: O2 Micro, Inc. Integrated MMC/SD Controller (rev 02) 48:03.3 Mass storage controller: O2 Micro, Inc. Integrated MS/xD Controller (rev 02) 48:03.4 FireWire (IEEE 1394): O2 Micro, Inc. Firewire (IEEE 1394) (rev 07) ff:00.0 Host bridge: Intel Corporation Core Processor QuickPath Architecture Generic Non-core Registers (rev 02) ff:00.1 Host bridge: Intel Corporation Core Processor QuickPath Architecture System Address Decoder (rev 02) ff:02.0 Host bridge: Intel Corporation Core Processor QPI Link 0 (rev 02) ff:02.1 Host bridge: Intel Corporation Core Processor QPI Physical...

...* It is not currently clear why this happens. A workaround + * is to use atomic instruction to store the new value. + */ + { + u16 lw = xchg(&qlock->lock_wait, _QSPINLOCK_LOCKED); + BUG_ON(lw != _QSPINLOCK_WAITING); + } + return 1; + } + return 0; +} + +/* + * With the qspinlock quickpath logic activated, disable the trylock logic + * in the slowpath as it will be redundant. + */ +#define queue_spin_trylock(lock) (0) #define queue_code_xchg queue_code_xchg /** @@ -131,13 +226,40 @@ static DEFINE_PER_CPU_ALIGNED(struct qnode_set, qnset) = { { { 0 } }, 0 }; * @lock : Pointer to...

On Tue, Jun 17, 2014 at 04:51:57PM -0400, Waiman Long wrote: > On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote: > >On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote: > >>Because the qspinlock needs to touch a second cacheline; add a pending > >>bit and allow a single in-word spinner before we punt to the second > >>cacheline. > >Could you

On Tue, Jun 17, 2014 at 04:51:57PM -0400, Waiman Long wrote: > On 06/17/2014 04:36 PM, Konrad Rzeszutek Wilk wrote: > >On Sun, Jun 15, 2014 at 02:47:00PM +0200, Peter Zijlstra wrote: > >>Because the qspinlock needs to touch a second cacheline; add a pending > >>bit and allow a single in-word spinner before we punt to the second > >>cacheline. > >Could you

...EMsk: RxErr+ BadTLP+ BadDLLP+ Rollover+ Timeout+ > NonFatalErr+ > AERCap: First Error Pointer: 00, GenCap+ CGenEn- > ChkCap+ ChkEn- > Capabilities: [180 v1] Power Budgeting <?> > Kernel modules: bfa > > fe:00.0 Host bridge: Intel Corporation QuickPath Architecture > Generic Non-core Registers (rev 02) > Subsystem: Intel Corporation Device 8086 > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- > ParErr- Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast > &g...

Hi, I''ve been trying to boot stefano''s minimal dom0 kernel from git://xenbits.xen.org/people/sstabellini/linux-pvhvm.git 2.6.36-rc1-initial-domain-v2+pat On xen-unstable, I get the following WARN_ON()''s from Xen when bringing up the NIC''s, then the machine hangs forever when trying to login either over serial or NIC. (XEN) Xen WARN at msi.c:649 (XEN) ----[

v5->v6: - Change the optimized 2-task contending code to make it fairer at the expense of a bit of performance. - Add a patch to support unfair queue spinlock for Xen. - Modify the PV qspinlock code to follow what was done in the PV ticketlock. - Add performance data for the unfair lock as well as the PV support code. v4->v5: - Move the optimized 2-task contending code to the

v5->v6: - Change the optimized 2-task contending code to make it fairer at the expense of a bit of performance. - Add a patch to support unfair queue spinlock for Xen. - Modify the PV qspinlock code to follow what was done in the PV ticketlock. - Add performance data for the unfair lock as well as the PV support code. v4->v5: - Move the optimized 2-task contending code to the

v6->v7: - Remove an atomic operation from the 2-task contending code - Shorten the names of some macros - Make the queue waiter to attempt to steal lock when unfair lock is enabled. - Remove lock holder kick from the PV code and fix a race condition - Run the unfair lock & PV code on overcommitted KVM guests to collect performance data. v5->v6: - Change the optimized

v6->v7: - Remove an atomic operation from the 2-task contending code - Shorten the names of some macros - Make the queue waiter to attempt to steal lock when unfair lock is enabled. - Remove lock holder kick from the PV code and fix a race condition - Run the unfair lock & PV code on overcommitted KVM guests to collect performance data. v5->v6: - Change the optimized