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Ugh, that would be a “yes” then… -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Krzysztof Parzyszek via llvm-dev Sent: Friday, September 27, 2019 10:05 AM To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.in>; llvm-dev at lists.llvm.o...

On Thu, Jun 18, 2020 at 3:37 PM Chris Tetreault <ctetreau at quicinc.com> wrote: > We’re talking about verbose output right? Verbose isn’t the default. > I'm fairly certain the issue in this thread is just the verbosity of -dump-input=fail. Yes, -vv makes it even more verbose by annotating input lines with good matches, etc., but that's not part...

...ailure, and doesn't show any cause for failure , so I run it in verbose mode with: bin/llvm-lit -a ../llvm/test/CodeGen/my_test.ll In a terminal, the new default behaviour of FileCheck has become pretty unusable IMHO. ________________________________ From: Chris Tetreault <ctetreau at quicinc.com> Sent: 18 June 2020 20:49 To: Joel E. Denny <jdenny.ornl at gmail.com> Cc: Sjoerd Meijer <Sjoerd.Meijer at arm.com>; llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org> Subject: RE: [llvm-dev] FileCheck Sjoerd specifically said “in verbose mode”, which I interpret to...

...n to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! ------------------&nbsp;Original&nbsp;------------------ From:&nbsp;"Krzysztof Parzyszek"<kparzysz at quicinc.com&gt;; Date:&nbsp;Fri, Nov 22, 2019 09:51 PM To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; Subject:&nbsp;RE: Re:RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation? Thanks. Looking at the InOperand...

...her def (1598) in statement (s1597), that’s why it’s needed. 2. The reason why the def of R11 in s1578 is not connected directly to the use in s1725 is that there may be an intervening def between them (that phi node of the register mask may be one such def). -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: Scott Douglas Constable <sdconsta at syr.edu> Sent: Friday, December 27, 2019 5:58 PM To: Krzysztof Parzyszek <kparzysz at quicinc.com> Cc: llvm-dev at lists.llvm.org Subject: [EXT] Re: [llvm-dev] Register Dataflow...

I don't remember the details of the particular case where we encountered this, but I think the loop started with the condition check and ended with an unconditional branch back to the beginning. -- Krzysztof Parzyszek  kparzysz at quicinc.com   LLVM compiler development -----Original Message----- From: Philip Reames <listmail at philipreames.com> Sent: Thursday, May 30, 2019 3:00 PM To: Krzysztof Parzyszek <kparzysz at quicinc.com>; Finkel, Hal J. <hfinkel at anl.gov>; Kit Barton <kit.barton at gmail.com>;...

..., That #1073741833 is a register mask. They are treated as aggregate registers (essentially sets of registers), so if it includes R9D and R11D, it will be treated as being aliased with both. These separate defs are there because they reach disjoint registers. -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: Scott Douglas Constable <sdconsta at syr.edu> Sent: Monday, December 23, 2019 2:10 PM To: Scott Douglas Constable <sdconsta at syr.edu> Cc: Krzysztof Parzyszek <kparzysz at quicinc.com>; llvm-dev at lists.llvm...

...file, and the current behaviour is already inconvenient, so don't see that as a solution. Cheers. ________________________________ From: Mehdi AMINI <joker.eph at gmail.com> Sent: 19 June 2020 09:32 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Chris Tetreault <ctetreau at quicinc.com>; Joel E. Denny <jdenny.ornl at gmail.com>; llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] FileCheck On Fri, Jun 19, 2020 at 12:56 AM Sjoerd Meijer via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:...

Thanks for the update, Phillips. Yes, please add me, Stephen and Ana (CCed) to Phabricator reviews. Zhaoshi From: Mitch Phillips <mitchp at google.com> Sent: Tuesday, July 14, 2020 19:10 To: Zhaoshi Zheng <zhaoshiz at quicinc.com> Cc: llvm-dev at lists.llvm.org; Stephen Long <steplong at quicinc.com> Subject: [EXT] Re: [llvm-dev] [MTE] Tagging Globals Hi Zhaoshi, Currently there's no global tagging instrumentation for MTE. We have a good idea about the implementation's design - but no patches are read...

Do you know whether it has been fixed on the 8.0.1 release? Scott On Fri, Nov 8, 2019 at 9:45 AM Krzysztof Parzyszek <kparzysz at quicinc.com<mailto:kparzysz at quicinc.com>> wrote: The one blocking issue that existed in the past has been fixed. I haven’t had time to do any work on it lately, but I’m not aware of any fundamental problems that would make it not work on x86. -- Krzysztof Parzyszek kparzysz at quicinc.com&lt...

...Defs = []; &nbsp; int CodeSize = 0; &nbsp; int AddedComplexity = 0; &nbsp; bit isReturn = 0; &nbsp; bit isBranch = 0; &nbsp; bit isEHScopeReturn = 0; ------------------&nbsp;Original&nbsp;------------------ From:&nbsp;"Krzysztof Parzyszek"<kparzysz at quicinc.com&gt;; Date:&nbsp;Fri, Nov 22, 2019 00:48 AM To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; Subject:&nbsp;RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation? Could you run llvm-tblgen with -print-rec...

I came across this thread from a couple years ago: http://lists.llvm.org/pipermail/llvm-dev/2017-November/119346.html Has there been any progress on RDF for X86? Or is there some other preferred alternative for performing reachability analysis after register allocation? Thanks, Scott Constable -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, In "target-features" list in LLVM-IR, there are "+feature", "-feature". My question is, does "-feature" is equivalent to not specifying a feature at all? For example: *attributes #0 = { "target-cpu"="znver2" "target-features"="+avx -avx2" }* Wheather it is equalent to omitting the avx2 from list? *attributes #0

...entry: unreachable exit: ; No predecessors! %tok = call token @llvm.bar() ret void } attributes #0 = { norecurse nounwind readnone } Where the remaining call is a wasted instruction. On Wed, Jun 17, 2020 at 12:28 PM Eli Friedman <efriedma at quicinc.com> wrote: > There’s no such thing as an “undef” token; you’ll get an assertion if you > try to create one. There is “none”, but the verifier will fail in some > cases if it sees a “none” token. > > > > In terms of actually erasing instructions, it’s specifically EHPad we...

...ds are i32, for example. > > Actual mixed types are less likely to happen, but if you are doing your > own target-specific lowering, you can end up with mixed types, simply > because your code doesn't have to make them all the same. > > -- > Krzysztof Parzyszek kparzysz at quicinc.com AI tools development > > > -----Original Message----- > > From: Cameron McInally <cameron.mcinally at nyu.edu> > > Sent: Tuesday, July 7, 2020 10:10 AM > > To: Krzysztof Parzyszek <kparzysz at quicinc.com> > > Cc: llvm-dev at lists.llvm.org > &g...

...020 at 10:58 AM Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Mixed integer types are ok, but the values will get truncated to the element type of the output value. It's pretty much what the comment says. > > -- > Krzysztof Parzyszek kparzysz at quicinc.com AI tools development > > > -----Original Message----- > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Cameron > > McInally via llvm-dev > > Sent: Tuesday, July 7, 2020 9:53 AM > > To: LLVM Developers Mailing List <llvm-dev at list...

> -----Original Message----- > From: Cameron McInally <cameron.mcinally at nyu.edu> > Sent: Friday, June 14, 2019 4:02 PM > To: Eli Friedman <efriedma at quicinc.com>; LLVM Developers Mailing List <llvm- > dev at lists.llvm.org> > Cc: Craig Topper <craig.topper at gmail.com>; Kaylor, Andrew > <andrew.kaylor at intel.com> > Subject: [EXT] Constrained integer DIV (WAS: Re: [llvm-dev] Planned change to > IR semantics: consta...

...y/work/llvm-project/llvm/lib/Target/RPP/RPPInstrInfo.td:565:3: error: In STOREbos: Input $rs1 must be an identifier! &nbsp; def bos : RPPInstMMEMrr<OPC_STORE, ------------------&nbsp;Original&nbsp;------------------ From:&nbsp;"Krzysztof Parzyszek"<kparzysz at quicinc.com&gt;; Date:&nbsp;Wed, Nov 20, 2019 09:59 PM To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; Subject:&nbsp;RE: Re:RE: [llvm-dev] Tablegen PAT limitation? Change //&nbsp; list<dag&gt; Patter...

...andling the cleanup of the stack in normal control flow (e.g. always for a normal call, and in the non-exceptional path for an invoke)? Then @llvm.call.preallocated.teardown is only necessary in the exceptional path to cleanup the stack. On Thu, Apr 16, 2020 at 1:40 PM Eli Friedman <efriedma at quicinc.com> wrote: > > > *From:* Reid Kleckner <rnk at google.com> > *Sent:* Thursday, April 16, 2020 1:06 PM > *To:* Eli Friedman <efriedma at quicinc.com> > *Cc:* Arthur Eubanks <aeubanks at google.com>; llvm-dev < > llvm-dev at lists.llvm.org> > *Subj...

...instructions. This solution has proved to work fine without having to explicitly involve the SR. Of course, the SR is still implicitly involved by the correct definition of ‘Uses’ and ‘Defs’ on the corresponding instructions. Joan Lluch > On 3 Jun 2019, at 21:00, Eli Friedman <efriedma at quicinc.com> wrote: > > Have you implemented TargetRegisterInfo::getCrossCopyRegClass? > > -Eli > > From: Joan Lluch <joan.lluch at icloud.com> > Sent: Sunday, June 2, 2019 2:39 AM > To: Eli Friedman <efriedma at quicinc.com> > Cc: llvm-dev <llvm-dev at li...