Displaying 7 results from an estimated 7 matches for "queue_info".
2015 Mar 11
0
[PATCH] pmu/gk20a: PMU boot support.
...truct pmu_init_msg_pmu_gk20a *init)
> +{
> + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *)
> + impl_from_pmu(pmu));
> + struct pmu_queue *queue = &pmu->queue[id];
> +
> + queue->id = id;
> + queue->index = init->queue_info[id].index;
> + queue->offset = init->queue_info[id].offset;
> + queue->size = init->queue_info[id].size;
> + queue->mutex_id = id;
> + mutex_init(&queue->mutex);
> +
> + nv_debug(ppmu, "queue %d: index %d, offset 0x%08x, s...
2015 Mar 11
3
[PATCH] pmu/gk20a: PMU boot support.
...u_seq_tbl);
+}
+
+static int pmu_queue_init(struct pmu_desc *pmu,
+ u32 id, struct pmu_init_msg_pmu_gk20a *init)
+{
+ struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *)
+ impl_from_pmu(pmu));
+ struct pmu_queue *queue = &pmu->queue[id];
+
+ queue->id = id;
+ queue->index = init->queue_info[id].index;
+ queue->offset = init->queue_info[id].offset;
+ queue->size = init->queue_info[id].size;
+ queue->mutex_id = id;
+ mutex_init(&queue->mutex);
+
+ nv_debug(ppmu, "queue %d: index %d, offset 0x%08x, size 0x%08x",
+ id, queue->index, queue->offset,...
2015 Mar 12
2
[PATCH] pmu/gk20a: PMU boot support.
...truct pmu_init_msg_pmu_gk20a *init)
> +{
> + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *)
> + impl_from_pmu(pmu));
> + struct pmu_queue *queue = &pmu->queue[id];
> +
> + queue->id = id;
> + queue->index = init->queue_info[id].index;
> + queue->offset = init->queue_info[id].offset;
> + queue->size = init->queue_info[id].size;
> + queue->mutex_id = id;
> + mutex_init(&queue->mutex);
> +
> + nv_debug(ppmu, "queue %d: index %d, offset 0x%08x, s...
2015 Apr 13
3
[PATCH v4] pmu/gk20a: PMU boot support
...u8 seq_id;
+};
+
+#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr)
+
+enum {
+ PMU_INIT_MSG_TYPE_PMU_INIT = 0,
+};
+
+/*pmu init msg format*/
+struct pmu_init_msg_pmu_gk20a {
+ u8 msg_type;
+ u8 pad;
+ u16 os_debug_entry_point;
+
+ struct {
+ u16 size;
+ u16 offset;
+ u8 index;
+ u8 pad;
+ } queue_info[PMU_QUEUE_COUNT];
+
+ u16 sw_managed_area_offset;
+ u16 sw_managed_area_size;
+};
+
+/*pmu init msg format*/
+struct pmu_init_msg {
+ union {
+ u8 msg_type;
+ struct pmu_init_msg_pmu_gk20a pmu_init_gk20a;
+ };
+};
+
+enum {
+ PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0,
+};
+
+struct pmu_rc_msg_unhandled_c...
2015 Apr 08
3
[PATCH V2] pmu/gk20a: PMU boot support.
...size;
+ u8 ctrl_flags;
+ u8 seq_id;
+};
+
+#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr)
+
+enum {
+ PMU_INIT_MSG_TYPE_PMU_INIT = 0,
+};
+
+struct pmu_init_msg_pmu_gk20a {
+ u8 msg_type;
+ u8 pad;
+ u16 os_debug_entry_point;
+
+ struct {
+ u16 size;
+ u16 offset;
+ u8 index;
+ u8 pad;
+ } queue_info[PMU_QUEUE_COUNT];
+
+ u16 sw_managed_area_offset;
+ u16 sw_managed_area_size;
+};
+
+struct pmu_init_msg {
+ union {
+ u8 msg_type;
+ struct pmu_init_msg_pmu_gk20a pmu_init_gk20a;
+ };
+};
+
+enum {
+ PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0,
+};
+
+struct pmu_rc_msg_unhandled_cmd {
+ u8 msg_type;
+ u8...
2015 Apr 30
2
[PATCH v4] pmu/gk20a: PMU boot support
...{
>> + u8 msg_type;
>> + u8 pad;
>> + u16 os_debug_entry_point;
>> +
>> + struct {
>> + u16 size;
>> + u16 offset;
>> + u8 index;
>> + u8 pad;
>> + } queue_info[PMU_QUEUE_COUNT];
>> +
>> + u16 sw_managed_area_offset;
>> + u16 sw_managed_area_size;
>> +};
>> +
>> +/*pmu init msg format*/
>> +struct pmu_init_msg {
>> + union {
>> + u8 msg_type;
>> + stru...
2016 Nov 21
33
[PATCH v4 0/33] Secure Boot refactoring / signed PMU firmware support for GM20B
This revision includes initial signed PMU firmware support for GM20B
(Tegra X1). This PMU code will also be used as a basis for dGPU signed
PMU firmware support.
With the PMU code, the refactoring of secure boot should also make
more sense.
ACR (secure boot) support is now separated by the driver version it
originates from. This separation allows to run any version of the ACR
on any chip,