Displaying 3 results from an estimated 3 matches for "q_sub".
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g_sub
2013 Jun 19
1
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
...ot;bit 31 set == lanes unresolvable" mode, and coalescing fails.
What about moving the lane masks to a BitVector, that wouldn't need to be
constrained artificially? Too much of a performance impact going that way?
I'd be open to any thoughts/suggestions. I studied the ARM
s_sub/d_sub/q_sub structure but that fits within the 32 bit lane mask. I
also thought that LDM/STM would be similar, but the registers are
physically enumerated, which is different from these virtual super reg
frames I'm trying to construct.
Thanks,
Joe
On Fri, May 31, 2013 at 5:00 PM, Jakob Stoklund Olesen...
2013 Jun 01
0
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
On May 31, 2013, at 4:59 PM, Joe Matarazzo <joe.matarazzo at gmail.com> wrote:
> I think the last time I pulled from trunk was probably end of last year. Some time ago. Does your reply intimate it's fixed on trunk?
Yes, it’s been fixed recently.
/jakob
2013 May 31
2
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
I think the last time I pulled from trunk was probably end of last year.
Some time ago. Does your reply intimate it's fixed on trunk? That would be
great. (I don't sync too often to avoid churn with my TD.)
Joe
On Fri, May 31, 2013 at 4:21 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
>
> On May 31, 2013, at 4:07 PM, Joe Matarazzo <joe.matarazzo at gmail.com>