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2009 Dec 05
2
[LLVMdev] use-def chain questions
...for virtual register
variables, however, I want to know if you also provide some kinds of use-def
chain for memory operations? for example, I have the following source code
int foo(int *q, int *p) {
int x;
*p = 1;
x = *q;
return x;
}
the IR after front-end is:
s1: store i32* %q, i32** %q_addr
s2: store i32* %p, i32** %p_addr
s3: %1 = load i32** %p_addr, align 8 ; <i32*> [#uses=1]
s4: store i32 1, i32* %1, align 4
s5: %2 = load i32** %q_addr, align 8 ; <i32*> [#uses=1]
s6: %3 = load i32* %2, align 4 ; <i32> [#uses=...
2009 Dec 05
0
[LLVMdev] use-def chain questions
...w if you also provide some kinds of use-def chain for memory operations? for example, I have the following source code
>
> int foo(int *q, int *p) {
> int x;
> *p = 1;
> x = *q;
> return x;
> }
>
> the IR after front-end is:
>
> s1: store i32* %q, i32** %q_addr
> s2: store i32* %p, i32** %p_addr
>
> s3: %1 = load i32** %p_addr, align 8 ; <i32*> [#uses=1]
> s4: store i32 1, i32* %1, align 4
>
> s5: %2 = load i32** %q_addr, align 8 ; <i32*> [#uses=1]
> s6: %3 = load i32* %2, align 4...