Displaying 20 results from an estimated 94 matches for "q8".
2019 Apr 19
1
haproxy + submission services -> postfix failure
...creen_upstream_proxy_timeout = 10s
That's it. I don't know what other information could be useful.
There are some logs, they are like this (I've got logging turned on
for pretty much every option I have:
Dovecot logs:
Apr 19 17:54:47 submission(__EMAIL__)<497><KUGA0OWG8XlfW/Q8>: Debug:
Added userdb setting: plugin/quota_rule=*:bytes=0
Apr 19 17:54:47 submission(__EMAIL__)<497><KUGA0OWG8XlfW/Q8>: Debug:
Effective uid=8, gid=8, home=/mail/__DOMAIN_COM__/__USER__
Apr 19 17:54:47 submission(__EMAIL__)<497><KUGA0OWG8XlfW/Q8>: Debug:
Namespace inbox:...
2002 Aug 20
2
weighting means
Hi everyone,
I've got a dataframe called 'faculty'. I want to do a weighted mean on
the column called 'Q8' weighted by the contents of column 'CETP'. In
addition, I need to operate on the result of splitting 'faculty'
according to the contents of a column 'FACULTY'. For example
> lapply(split(faculty$Q8, faculty$FACULTY), mean)
$"1"
[1] 2.2
$"2"
[1]...
2005 Nov 12
1
computation on a table
Hello,
I have a table (1) of the form
q1 q3 q4 q8 q9
A 5 2 0 1 3
B 2 0 2 4 4
I have another table (2):
q1 q2 q3 q4 q5 q6 q7 q8 q9
C 10 7 4 2 6 9 3 1 2
I would like to divide the numbers in table (1) by the number of the
appropriate column in table (2):
q1 q3 q4 q8 q9
A 5/10 2/4 0/2 1...
2002 Jul 27
1
ABX at q8
...of all, 100x thanks to Monty and colleagues: you have done an
excellent job! I just didn't believe my ears when I first tested Oggenc
1.0 at q0 to q1 - it sounds AMAZINGLY GOOD !!!
But as HDD drives are getting larger and cheaper, most of us move toward
higher quality settings ......... I use q8, because:
- I was able to ABX some test samples up to q4.99
- at q8 Ogg is still around 3.5x smaller than lossless
- it sounds perfect to me!!
I was just courious to know if anyone out there is able to distinguish
from the original (ABX) Vorbis 1.0 at around q8 (or q7 to q9) on "NORMAL
MUSIC&...
2012 May 11
1
Strange "Error: subscript out of bounds"
...quot;, las=1, main=titles[n])
axis(1)
axis(2)
lines(1:5, pred.mat[k+1,], lty=1)
lines(1:5, pred.mat[k+2,], lty=3)
legend("topright", c("avg. player", "5th %-tile player", "95th %-tile
player"), lty=1:3, bty="n")
n<-n+1
}
}
plotProb(q8.pred.mat.v13, c(193, 196, 199, 205, 217,241,289), c(3,3),
q8.titles3, "identification")
[1] "debug"
[1] 193
[1] 1
[1] 1920
Error in print(pred.mat[k, ]) :
error in evaluating the argument 'x' in selecting a method for
function 'print': Error: subscript out o...
2011 Jul 06
3
Tables and merge
...Q1.rec')
> q2 = read.epiinfo('Dados/Q2.rec')
> q3 = read.epiinfo('Dados/Q3.rec')
> q4 = read.epiinfo('Dados/Q4.rec')
> q5 = read.epiinfo('Dados/Q5.rec')
> q6 = read.epiinfo('Dados/Q6.rec')
> q7 = read.epiinfo('Dados/Q7.rec')
> q8 = read.epiinfo('Dados/Q8.rec')
>
> juntos = merge(q1,q2,q3,q4,q5,q6,q7,q8)
>
> But it didn't work. Any suggestions?
>
> Thank you.
>
> --------------------------------------
> Silvano Cesar da Costa
> Departamento de Estat?stica
> Universidade Estadual d...
2011 Sep 01
0
[PATCH 5/5] resample: Add NEON optimized inner_product_single for floating point
...inner_product_single(const float *a, const float *b, unsigned int len)
+{
+ float ret;
+ uint32_t remainder = len % 16;
+ len = len - remainder;
+
+ asm volatile (" cmp %[len], #0\n"
+ " bne 1f\n"
+ " vld1.32 {q4}, [%[b]]!\n"
+ " vld1.32 {q8}, [%[a]]!\n"
+ " subs %[remainder], %[remainder], #4\n"
+ " vmul.f32 q0, q4, q8\n"
+ " bne 4f\n"
+ " b 5f\n"
+ "1:"
+ " vld1.32 {q4, q5}, [%[b]]!\n"
+ " vld1.32 {q8, q9}, [%[a]]!\n"
+ "...
2011 Feb 04
1
imagemagick 6.6.7.4-Q8
which rmagick gem configured with imagemagick6.6.7.4-Q8
please reply...m not getting in google
--
Posted via http://www.ruby-forum.com/.
--
You received this message because you are subscribed to the Google Groups "Ruby on Rails: Talk" group.
To post to this group, send email to rubyonrails-talk-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gman...
2013 Oct 14
1
[LLVMdev] Vectorization of pointer PHI nodes
...test.c:11: note: === vect_do_peeling_for_loop_bound ===Setting upper bound
of nb iterations for epilogue loop to 14
test.c:11: note: LOOP VECTORIZED.
The result is a very concise and very dense code:
vld1.8 {d28[], d29[]}, [r5]
vld3.8 {d16, d18, d20}, [r9]!
vld3.8 {d17, d19, d21}, [r9]
vmvn q3, q8
vmvn q15, q9
vmvn q8, q10
vsub.i8 q11, q3, q14
vsub.i8 q12, q15, q14
vsub.i8 q13, q8, q14
vst3.8 {d22, d24, d26}, [r8]!
vst3.8 {d23, d25, d27}, [r8]
cheers,
--renato
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attac...
2014 Dec 07
3
[LLVMdev] NEON intrinsics preventing redundant load optimization?
...* b.data[i];
return result;
}
void TestVec4Multiply(vec4& a, vec4& b, vec4& result)
{
result = a * b;
}
With -O3 the loop gets vectorized and the code generated looks optimal:
__Z16TestVec4MultiplyR4vec4S0_S0_:
@ BB#0:
vld1.32 {d16, d17}, [r1]
vld1.32 {d18, d19}, [r0]
vmul.f32 q8, q9, q8
vst1.32 {d16, d17}, [r2]
bx lr
However if I replace the operator* with a NEON intrinsic implementation (I know the vectorizer figured out optimal code in this case anyway, but that wasn't true for my real situation) then the temporary "result" seems to be kept in the genera...
2013 May 21
0
[PATCH] 02-
...6 samples at a time */
+ "movs %5, %3, lsr #4;\n"
+ "beq .celt_fir1_process16_done_%=;\n"
+
+ ".celt_fir1_process16_%=:\n"
+ /* Load 16 x values in q0, q1 lanes */
+ "vld1.16 {q0-q1}, [%0]!;\n"
+
+ /* Init four 32 bits sum in q7, q8, q9, q10 lanes */
+ "vshll.s16 q7, d0, %[SIGSHIFT];\n"
+ "vshll.s16 q8, d1, %[SIGSHIFT];\n"
+ "vshll.s16 q9, d2, %[SIGSHIFT];\n"
+ "vshll.s16 q10, d3, %[SIGSHIFT];\n"
+
+ /* Make previous samples vector for MAC in q5, q6 lanes */
+...
2002 Aug 22
1
combining output from several operations
...ow is that I need the describe
function (from the Hmisc library) to give me the standard deviation
as well as the mean. Is it possible to do that without modifying the
describe function directly?
I'd be glad to hear any suggestions from the R gurus on the list.
-Tim
> lapply(split(faculty$Q8, list(faculty$TWOYROR4, faculty$FACULTY)),
describe)
$"2.1"
X[[1]]
n missing unique Mean
47 0 3 3.362
3 (38, 81%), 4 (1, 2%), 5 (8, 17%)
$"4.1"
X[[2]]
n missing unique Mean
147 0 5 1.837
0 1 2 3 4
Fr...
2012 Sep 21
5
[LLVMdev] Question about LLVM NEON intrinsics
...>* %C
ret void
}
declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
I've got following code generated:
...
vmaxf32: @ @vmaxf32
@ BB#0:
vld1.64 {d16, d17}, [r2]
vld1.64 {d18, d19}, [r1]
vmax.f32 q8, q9, q8
vst1.64 {d16, d17}, [r0]
bx lr
...
Now if use <16 x float> vectors instead of <4 x float>:
define void @vmaxf32(<16 x float> *%C, <16 x float>* %A, <16 x float>* %B) nounwind {
%tmp1 = load <16 x float>* %A
%tmp2 = load <16 x float>* %B...
2013 May 21
2
[PATCH] 02-Add CELT filter optimizations
...6 samples at a time */
+ "movs %5, %3, lsr #4;\n"
+ "beq .celt_fir1_process16_done_%=;\n"
+
+ ".celt_fir1_process16_%=:\n"
+ /* Load 16 x values in q0, q1 lanes */
+ "vld1.16 {q0-q1}, [%0]!;\n"
+
+ /* Init four 32 bits sum in q7, q8, q9, q10 lanes */
+ "vshll.s16 q7, d0, %[SIGSHIFT];\n"
+ "vshll.s16 q8, d1, %[SIGSHIFT];\n"
+ "vshll.s16 q9, d2, %[SIGSHIFT];\n"
+ "vshll.s16 q10, d3, %[SIGSHIFT];\n"
+
+ /* Make previous samples vector for MAC in q5, q6 lanes */
+...
2012 Jul 05
2
[LLVMdev] RE : Vector argument passing abi for ARM ?
...code contains a misaligned load:
bar: @ @bar
@ BB#0: @ %L.entry
push {r11, lr}
add r0, r1, #2
vldr s0, [r1]
vldr s2, [r0] # <= here load is misaligned
vmovl.u8 q8, d0
vmovl.u8 q9, d1
vmovl.u16 q8, d16
vmovl.u16 q9, d18
vmov r0, r1, d16
vmov r2, r3, d18
bl zzz(PLT)
pop {r11, pc}
with LLVM trunk, assembly looks like:
bar: @ @bar
@ BB#0: @ %L.entry...
2012 Sep 06
1
[LLVMdev] Unaligned vector memory access for ARM/NEON.
...le that it's LLVM that's confused about the alignment requirements here. :)
>
> I think I see, in general, where. I twiddled the IR to give it higher alignment (16 bytes) and get:
> extend: @ @extend
> @ BB#0:
> vldr d16, [r0]
> vmovl.s16 q8, d16
> vstmia r1, {d16, d17}
> vldr d16, [r0, #8]
> add r0, r1, #16
> vmovl.s16 q8, d16
> vstmia r0, {d16, d17}
> bx lr
>
> Note that we're using a plain vldr instruction here to load the d register, not a vld1 instruction. Similarly for the stores. According to t...
2012 Sep 21
0
[LLVMdev] Question about LLVM NEON intrinsics
....v4f32(<4 x float>, <4 x float>) nounwind readnone
>
> I've got following code generated:
>
> ...
> vmaxf32: @ @vmaxf32
> @ BB#0:
> vld1.64 {d16, d17}, [r2]
> vld1.64 {d18, d19}, [r1]
> vmax.f32 q8, q9, q8
> vst1.64 {d16, d17}, [r0]
> bx lr
> ...
>
> Now if use <16 x float> vectors instead of <4 x float>:
>
> define void @vmaxf32(<16 x float> *%C, <16 x float>* %A, <16 x float>* %B) nounwind {
> %tmp1 = load <16...
2012 Jul 05
0
[LLVMdev] RE : Vector argument passing abi for ARM ?
...load:
>
> bar: @ @bar
> @ BB#0: @ %L.entry
> push {r11, lr}
> add r0, r1, #2
> vldr s0, [r1]
> vldr s2, [r0] # <= here load is misaligned
> vmovl.u8 q8, d0
> vmovl.u8 q9, d1
> vmovl.u16 q8, d16
> vmovl.u16 q9, d18
> vmov r0, r1, d16
> vmov r2, r3, d18
> bl zzz(PLT)
> pop {r11, pc}
>
> with LLVM trunk, assembly looks like:
>
> bar: @...
2012 Sep 05
0
[LLVMdev] Unaligned vector memory access for ARM/NEON.
...Well, it's entirely possible that it's LLVM that's confused about the alignment requirements here. :)
I think I see, in general, where. I twiddled the IR to give it higher alignment (16 bytes) and get:
extend: @ @extend
@ BB#0:
vldr d16, [r0]
vmovl.s16 q8, d16
vstmia r1, {d16, d17}
vldr d16, [r0, #8]
add r0, r1, #16
vmovl.s16 q8, d16
vstmia r0, {d16, d17}
bx lr
Note that we're using a plain vldr instruction here to load the d register, not a vld1 instruction. Similarly for the stores. According to the ARM ARM (DDI 0406C), you're corr...
2012 Sep 21
2
[LLVMdev] RE : Question about LLVM NEON intrinsics
....v4f32(<4 x float>, <4 x float>) nounwind readnone
>
> I've got following code generated:
>
> ...
> vmaxf32: @ @vmaxf32
> @ BB#0:
> vld1.64 {d16, d17}, [r2]
> vld1.64 {d18, d19}, [r1]
> vmax.f32 q8, q9, q8
> vst1.64 {d16, d17}, [r0]
> bx lr
> ...
>
> Now if use <16 x float> vectors instead of <4 x float>:
>
> define void @vmaxf32(<16 x float> *%C, <16 x float>* %A, <16 x float>* %B) nounwind {
> %tmp1 = load <16...