search for: q14

Displaying 20 results from an estimated 30 matches for "q14".

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2012 Nov 12
3
select different variables from a list of data frames
...ferent variables from a list of data frames. I have a list of 13 that looks like below. Each data frame has more variables than I need. How do I go through the list and select the variables that I need. In the example below, I need to get the variables "a", and "q10" and "q14" to be returned to two separate data frames. Thank you. Yours, Simon Kiss #####Sample data mylist<-list(df1=data.frame(a=seq(1,10,1), c=seq(1,109,1), q10=rep('favour', 10)), df2=data.frame(a=seq(1,10,1), b=seq(15,24,1), q14=rep('favour', 10))) #The variables with differe...
2013 Oct 14
1
[LLVMdev] Vectorization of pointer PHI nodes
...ound ===Setting upper bound of nb iterations for epilogue loop to 14 test.c:11: note: LOOP VECTORIZED. The result is a very concise and very dense code: vld1.8 {d28[], d29[]}, [r5] vld3.8 {d16, d18, d20}, [r9]! vld3.8 {d17, d19, d21}, [r9] vmvn q3, q8 vmvn q15, q9 vmvn q8, q10 vsub.i8 q11, q3, q14 vsub.i8 q12, q15, q14 vsub.i8 q13, q8, q14 vst3.8 {d22, d24, d26}, [r8]! vst3.8 {d23, d25, d27}, [r8] cheers, --renato -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131014/a05ed9f0/attachment.html> ----...
2007 Feb 20
0
Standardized residual variances in SEM
...0.0e+00 Q9 <--- G param10 0.64 0.065 9.9 0.0e+00 Q10 <--- G param11 0.72 0.054 13.3 0.0e+00 Q11 <--- G param12 0.59 0.063 9.3 0.0e+00 Q12 <--- G param13 0.61 0.069 8.7 0.0e+00 Q13 <--- G param14 0.70 0.074 9.6 0.0e+00 Q14 <--- G param15 0.68 0.066 10.4 0.0e+00 Q15 <--- G param16 0.75 0.056 13.3 0.0e+00 Q16 <--- G param17 0.86 0.060 14.3 0.0e+00 Q17 <--- G param18 0.63 0.059 10.7 0.0e+00 Q18 <--- G param19 0.75 0.062 12.2 0.0e+00 Q19 <--- G...
2009 Nov 12
1
Transforming a dataframe into a response/predictor matrix
...: Lastname Firstname CATALOG_NBR Email StudentID EMPLID Start 1 alastname afirstname 1213 *@uark.edu 10295236 # 12/2/2008 2 anotherlastname anotherfirstname 1213 **@uark.edu ## 10295236 9/3/2008 Xattempts Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 1 2 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 Score Form CRSE_GRADE_OFF 1 0 0 0 0 0 0 0 0 0 1...
2013 Oct 14
0
[LLVMdev] Vectorization of pointer PHI nodes
Renato, can you post the c code for the function and the assembly that gcc produces? Your initial example could be well handled by vectorization of strided loops (and the mentioning of VLD3(.8?)/VST3(.8?) lead me to assume that this is what happened). But the LLVM-IR you sent has a store of 0 in there ;) and strides by 4. Thanks, Arnold Vectorization of strided loops: I am using float as the
2002 Aug 01
2
mdct.h - PI1_8, PI2_8 etc.
..._8 .38268343236508977175F #define cPI2_8 .70710678118654752441F #define cPI1_8 .92387953251128675613F #define FLOAT_CONV(x) = x Could someone explain where these values come from? What's the significance of TRIGBITS? It seems that the integer values are related to the floating point values by q14 representation (multiply by 2^14 to get the integer values) but why chose q14? Why the subscript _8? And what do PI1, PI2, PI3 represent? Hope someone can shed some light on this for me! Gov <p>--- >8 ---- List archives: http://www.xiph.org/archives/ Ogg project homepage: http://www....
2012 Nov 25
1
Iterate by Factor - Newbie Question
I have end of semester teaching evaluation data of the following form: > head(evaluations) Course Prefix Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 1 2330301 2 4 3 3 3 4 4 1 2 5 4 1 1 1 1 2 2330301 2 3 3 3 3 3 5 1 2 5 8 1 1 1 1 3 2330301 2 4 4 3 3 4 4 2 2 5 9 1 1 1 1 4 2330301 2 2 1 1 3 4 5 1 2 5 8 1 1 1 1 5 2330301 2 4 3 4 4 4 3 1 3 5...
2013 Oct 14
4
[LLVMdev] Vectorization of pointer PHI nodes
This is almost ideal for SLP vectorization, except for two problems: 1. We have 4 stores to consecutive locations, but the last element is the constant zero, and not an additional SUB. At the moment we don’t have support for idempotence operations, but this is something that we should add. 2. The values that we are subtracting come from 3 loads. We usually load 4 elements from memory, or
2011 Apr 15
2
Function for deleting variables with >=50% missing obs from a data frame
...ple, Q1 in one of my data frames has over 66% of its observations missing. I have tried imputation with mice but it does not work for all the data frames and I get the following message or a similar message to this: iter imp variable 1 1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q19 Q36 Q47 Q52 Q79 Q80 Q94 Q97 Q104 Q108 Q122 Q131 Q134 P1 P2 P3 P4 P5 P6Error in solve.default(xtx + diag(pen)) : system is computationally singular: reciprocal condition number = 1.83044e-16 In addition: Warning messages: 1: In sqrt((sum(residuals^2))/(sum(ry) - ncol(x...
2015 Aug 05
0
[PATCH 8/8] Apply Neon short prediction optimization to silk_noise_shape_quantizer_del_dec.
.../NSQ_del_dec.c b/silk/NSQ_del_dec.c index aff560c..aaa1fca 100644 --- a/silk/NSQ_del_dec.c +++ b/silk/NSQ_del_dec.c @@ -31,6 +31,8 @@ POSSIBILITY OF SUCH DAMAGE. #include "main.h" #include "stack_alloc.h" +#include "NSQ.h" + typedef struct { opus_int32 sLPC_Q14[ MAX_SUB_FRAME_LENGTH + NSQ_LPC_BUF_LENGTH ]; @@ -106,7 +108,8 @@ static OPUS_INLINE void silk_noise_shape_quantizer_del_dec( opus_int warping_Q16, /* I */ opus_int nStatesDelayedDecision, /* I Number of states in...
2015 Nov 21
0
[Aarch64 v2 07/18] Apply Neon short prediction optimization to silk_noise_shape_quantizer_del_dec.
.../NSQ_del_dec.c b/silk/NSQ_del_dec.c index aff560c..aaa1fca 100644 --- a/silk/NSQ_del_dec.c +++ b/silk/NSQ_del_dec.c @@ -31,6 +31,8 @@ POSSIBILITY OF SUCH DAMAGE. #include "main.h" #include "stack_alloc.h" +#include "NSQ.h" + typedef struct { opus_int32 sLPC_Q14[ MAX_SUB_FRAME_LENGTH + NSQ_LPC_BUF_LENGTH ]; @@ -106,7 +108,8 @@ static OPUS_INLINE void silk_noise_shape_quantizer_del_dec( opus_int warping_Q16, /* I */ opus_int nStatesDelayedDecision, /* I Number of states in...
2016 Aug 23
0
[PATCH 8/8] Optimize silk_NSQ_del_dec() for ARM NEON
...*/ + opus_int8 pulses[], /* O Quantized pulse signal */ + const opus_int16 PredCoef_Q12[ 2 * MAX_LPC_ORDER ], /* I Short term prediction coefs */ + const opus_int16 LTPCoef_Q14[ LTP_ORDER * MAX_NB_SUBFR ], /* I Long term prediction coefs */ + const opus_int16 AR_Q13[ MAX_NB_SUBFR * MAX_SHAPE_LPC_ORDER ], /* I Noise shaping coefs */ + const opus_int HarmShapeGain_Q14[ MAX_NB_SUBFR ], /* I Long term shaping c...
2016 Aug 23
2
[PATCH 7/8] Update NSQ_LPC_BUF_LENGTH macro.
NSQ_LPC_BUF_LENGTH is independent of DECISION_DELAY. --- silk/define.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/silk/define.h b/silk/define.h index 781cfdc..1286048 100644 --- a/silk/define.h +++ b/silk/define.h @@ -173,11 +173,7 @@ extern "C" #define MAX_MATRIX_SIZE MAX_LPC_ORDER /* Max of LPC Order and LTP order */ -#if( MAX_LPC_ORDER >
2012 Sep 21
0
[LLVMdev] Question about LLVM NEON intrinsics
On 21 September 2012 09:28, Sebastien DELDON-GNB <sebastien.deldon at st.com> wrote: > declare <16 x float> @llvm.arm.neon.vmaxs.v16f32(<16 x float>, <16 x float>) nounwind readnone > > llc fails with following message: > > SplitVectorResult #0: 0x2258350: v16f32 = llvm.arm.neon.vmaxs 0x2258250, 0x2258050, 0x2258150 [ORD=3] [ID=0] > > LLVM ERROR: Do not
2013 Feb 21
3
Having trouble converting a dataframe of character vectors to factors
R Experts, I have a dataframe made up of character vectors--these are results from survey questions. I need to convert them to factors. I tried the following which did not work: scs2<-sapply(scs2,as.factor) also this didn't work: scs2<-sapply(scs2,function(x) as.factor(x)) After doing either of above I end up with >str(scs2) chr [1:10, 1:10] "very important" "very
2012 Sep 21
2
[LLVMdev] RE : Question about LLVM NEON intrinsics
...r3, :128] add r3, r2, #48 vld1.64 {d16, d17}, [r2, :128] add r2, r2, #16 vld1.64 {d18, d19}, [r1, :128] vld1.64 {d26, d27}, [r12, :128] add r12, r1, #32 vld1.64 {d24, d25}, [r3, :128] add r1, r1, #16 vadd.f32 q11, q9, q8 vld1.64 {d28, d29}, [r12, :128] vadd.f32 q9, q13, q12 vadd.f32 q8, q14, q10 vld1.64 {d20, d21}, [r2, :128] vld1.64 {d24, d25}, [r1, :128] add r1, r0, #48 vadd.f32 q10, q12, q10 vst1.64 {d22, d23}, [r0, :128] vst1.64 {d18, d19}, [r1, :128] add r1, r0, #32 add r0, r0, #16 vst1.64 {d16, d17}, [r1, :128] vst1.64 {d20, d21}, [r0, :128] bx lr .Ltmp0: .size vaddf...
2008 Jul 03
1
Migrating from S-Plus to R - Exporting Tables
...gt; 3 256.44 352.71 > 4 237.78 317.62 > tot 251.35 354.49 > > and nomequest is a vector >> nomequest04 > [1] "Q05" "Q06" "Q07" "Q08" "Q09" "Q10" "Q11" "Q12" > [9] "Q14" "Q15" "NESCPM" > > > > > > > I want to export an table using the write.table and i want is this format: > (this table was exported in s-plus) > > Q01 > row.names Num Perc meab stdev min > A 10237 4...
2012 Sep 21
5
[LLVMdev] Question about LLVM NEON intrinsics
Hi all, I would like to know if LLVM Neon intrinsics are designed to support only 'Legal' types for NEON units. Using llc -march=arm -mcpu=cortex-a9 vmax4.ll -o vmax4.s on following ll code: ; ModuleID = 'vmax.ll' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" target triple =
2015 Dec 23
6
[AArch64 neon intrinsics v4 0/5] Rework Neon intrinsic code for Aarch64 patchset
Following Tim's comments, here are my reworked patches for the Neon intrinsic function patches of of my Aarch64 patchset, i.e. replacing patches 5-8 of the v2 series. Patches 1-4 and 9-18 of the old series still apply unmodified. The one new (as opposed to changed) patch is the first one in this series, to add named constants for the ARM architecture variants. There are also some minor code
2015 Nov 21
12
[Aarch64 v2 00/18] Patches to enable Aarch64 (version 2)
As promised, here's a re-send of all my Aarch64 patches, following comments by John Ridges. Note that they actually affect more than just Aarch64 -- other than the ones specifically guarded by AARCH64_NEON defines, the Neon intrinsics all also apply on armv7; and the OPUS_FAST_INT64 patches apply on any 64-bit machine. The patches should largely be independent and independently useful, other