Displaying 20 results from an estimated 38 matches for "q12".
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2010 Apr 07
2
recoding variables-recode not working
Hi,
I have numerical variable that I want to recode into categories '0' and '1
and more' and do analysis with that data.
I have tried various of possibilities to do so, but I am sucked and nothing
is working.
recode(Q12, "0='A';1:30='B'")
cut(Q12, breaks=c(0,1,30), lables=c('0', '1 and more'))
cat(Q12, "0=0;1-33=1")
What should I do to make it right?
--
**************************
Vlatka
[[alternative HTML version deleted]]
2012 Apr 13
1
R: Colouring phylogenetic tip labels and/or edges
...ates<-structure(states$PC, names=states$Species)
names(states)<-tree$tip.label
#MuSSE
diversitree:::argnames.musse(NULL, 3) #number of states
lik<-make.musse(tree, states, 3)
argnames(lik)
#contstrain lambda
lik.base<-constrain(lik, lambda2~lambda1, lambda3~lambda1, mu2~mu1,mu3~mu1,q13~q12,q21~q12,q23~q12,q31~q12,q32~q12)
#find ML point for this model
p<-starting.point.musse(tree, 3)
fit.base<-find.mle(lik.base, p[argnames(lik.base)])
#unconstrained
lik.lambda<-constrain(lik,mu2~mu1,mu3~mu1,q13~q12,q21~q12,q23~q12,q31~q12,q32~q12)
fit.lambda<-find.mle(lik.lambda, p[argna...
2007 Feb 20
0
Standardized residual variances in SEM
...0.0e+00 Q6 <--- G
param7 0.65 0.060 11.0 0.0e+00 Q7 <--- G
param9 0.60 0.059 10.1 0.0e+00 Q9 <--- G
param10 0.64 0.065 9.9 0.0e+00 Q10 <--- G
param11 0.72 0.054 13.3 0.0e+00 Q11 <--- G
param12 0.59 0.063 9.3 0.0e+00 Q12 <--- G
param13 0.61 0.069 8.7 0.0e+00 Q13 <--- G
param14 0.70 0.074 9.6 0.0e+00 Q14 <--- G
param15 0.68 0.066 10.4 0.0e+00 Q15 <--- G
param16 0.75 0.056 13.3 0.0e+00 Q16 <--- G
param17 0.86 0.060 14.3 0.0e+00 Q17 <--- G...
2016 Jul 30
2
Cannot compile speexdsp 1.2rc3 on ARM64
...ot; (ret)
> : [a] "w" (a)
> : "v0" );
> return ret;
> }
> #elif defined(__ARM_NEON__)
> static inline int32_t saturate_32bit_to_16bit(int32_t a) {
> int32_t ret;
> asm volatile ("vmov.s32 d24[0], %[a]\n"
> "vqmovn.s32 d24, q12\n"
> "vmov.s16 %[ret], d24[0]\n"
> : [ret] "=&r" (ret)
> : [a] "r" (a)
> : "q12", "d24", "d25" );
> return ret;
> }
> #else
> static inline int32_t saturate_32bit_to_16bit(int32_t a) {
&...
2016 Jul 28
0
[PATCH] Optimize silk_LPC_analysis_filter() for ARM NEON
..., /* O Output signal */
const opus_int16 *in, /* I Input signal */
const opus_int16 *B, /* I MA prediction coefficients, Q12 [order] */
@@ -74,9 +73,6 @@ void silk_LPC_analysis_filter(
num[ j ] = -B[ j ];
}
celt_fir( in + d, num, out + d, len - d, d, arch );
- for ( j = 0; j < d; j++ ) {
- out[ j ] = 0;
- }
#else
(void)arch;
for( ix = d; ix < len; ix++...
2009 Nov 12
1
Transforming a dataframe into a response/predictor matrix
...wn below:
Lastname Firstname CATALOG_NBR Email StudentID EMPLID Start
1 alastname afirstname 1213 *@uark.edu 10295236 # 12/2/2008
2 anotherlastname anotherfirstname 1213 **@uark.edu ## 10295236 9/3/2008
Xattempts Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19
1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 1
2 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1
Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 Score Form CRSE_GRADE_OFF
1 0 0 0 0 0 0 0 0...
2017 Apr 26
2
2 patches related to silk_biquad_alt() optimization
...gt; 1 */
)
{
/* DIRECT FORM II TRANSPOSED (uses 2 element state vector) */
opus_int k;
silk_assert( ( stride == 1 ) || ( stride == 2 ) );
if( stride == 1) {
opus_int32 out32_Q14;
for( k = 0; k < len; k++ ) {
/* S[ 0 ], S[ 1 ]: Q12 */
out32_Q14 = silk_LSHIFT( silk_SMLAWB( S[ 0 ], B_Q28[ 0 ], in[ k
] ), 2 );
S[ 0 ] = S[ 1 ] + silk_RSHIFT_ROUND( (opus_int64)out32_Q14 *
(-A_Q28[ 0 ]), 30 );
S[ 0 ] = silk_SMLAWB( S[ 0 ], B_Q28[ 1 ], in[ k ] );
S[ 1 ] = silk_RSHIFT_ROUND( (opus_int...
2015 Mar 28
4
Cannot compile speexdsp 1.2rc3 on ARM64
Hi all,
I build successfully with speex-1.2rc2. And with speexdsp 1.2rc3, I
build with i386, X86_64, armv7 and armv7s all passed.
But when I build for ARM64 (for iPhone 6), it failed with:
/Applications/Xcode.app/Contents/Developer/usr/bin/make all-recursive
Making all in libspeexdsp
CC preprocess.lo
CC jitter.lo
CC mdf.lo
CC fftwrap.lo
CC
2017 May 15
2
2 patches related to silk_biquad_alt() optimization
...SED (uses 2 element state vector) */
> opus_int k;
>
> silk_assert( ( stride == 1 ) || ( stride == 2 ) );
>
> if( stride == 1) {
> opus_int32 out32_Q14;
> for( k = 0; k < len; k++ ) {
> /* S[ 0 ], S[ 1 ]: Q12 */
> out32_Q14 = silk_LSHIFT( silk_SMLAWB( S[ 0 ], B_Q28[ 0
> ], in[ k ] ), 2 );
>
> S[ 0 ] = S[ 1 ] + silk_RSHIFT_ROUND(
> (opus_int64)out32_Q14 * (-A_Q28[ 0 ]), 30 );
> S[ 0 ] = silk_SMLAWB( S[ 0 ], B_Q28[ 1 ], in[ k ] );...
2016 Apr 19
0
Cannot compile speexdsp 1.2rc3 on ARM64
...et], s0\n"
: [ret] "=&r" (ret)
: [a] "w" (a)
: "v0" );
return ret;
}
#elif defined(__ARM_NEON__)
static inline int32_t saturate_32bit_to_16bit(int32_t a) {
int32_t ret;
asm volatile ("vmov.s32 d24[0], %[a]\n"
"vqmovn.s32 d24, q12\n"
"vmov.s16 %[ret], d24[0]\n"
: [ret] "=&r" (ret)
: [a] "r" (a)
: "q12", "d24", "d25" );
return ret;
}
#else
static inline int32_t saturate_32bit_to_16bit(int32_t a) {
return max(-32768, min(32767, a));
}
#end...
2016 Aug 09
0
Cannot compile speexdsp 1.2rc3 on ARM64
...w" (a)
>> : "v0" );
>> return ret;
>> }
>> #elif defined(__ARM_NEON__)
>> static inline int32_t saturate_32bit_to_16bit(int32_t a) {
>> int32_t ret;
>> asm volatile ("vmov.s32 d24[0], %[a]\n"
>> "vqmovn.s32 d24, q12\n"
>> "vmov.s16 %[ret], d24[0]\n"
>> : [ret] "=&r" (ret)
>> : [a] "r" (a)
>> : "q12", "d24", "d25" );
>> return ret;
>> }
>> #else
>> static inline int32_t satura...
2013 Oct 14
1
[LLVMdev] Vectorization of pointer PHI nodes
...ing upper bound
of nb iterations for epilogue loop to 14
test.c:11: note: LOOP VECTORIZED.
The result is a very concise and very dense code:
vld1.8 {d28[], d29[]}, [r5]
vld3.8 {d16, d18, d20}, [r9]!
vld3.8 {d17, d19, d21}, [r9]
vmvn q3, q8
vmvn q15, q9
vmvn q8, q10
vsub.i8 q11, q3, q14
vsub.i8 q12, q15, q14
vsub.i8 q13, q8, q14
vst3.8 {d22, d24, d26}, [r8]!
vst3.8 {d23, d25, d27}, [r8]
cheers,
--renato
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2012 Sep 21
0
[LLVMdev] Question about LLVM NEON intrinsics
On 21 September 2012 09:28, Sebastien DELDON-GNB
<sebastien.deldon at st.com> wrote:
> declare <16 x float> @llvm.arm.neon.vmaxs.v16f32(<16 x float>, <16 x float>) nounwind readnone
>
> llc fails with following message:
>
> SplitVectorResult #0: 0x2258350: v16f32 = llvm.arm.neon.vmaxs 0x2258250, 0x2258050, 0x2258150 [ORD=3] [ID=0]
>
> LLVM ERROR: Do not
2012 Nov 25
1
Iterate by Factor - Newbie Question
I have end of semester teaching evaluation data of the following form:
> head(evaluations)
Course Prefix Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14
1 2330301 2 4 3 3 3 4 4 1 2 5 4 1 1 1 1
2 2330301 2 3 3 3 3 3 5 1 2 5 8 1 1 1 1
3 2330301 2 4 4 3 3 4 4 2 2 5 9 1 1 1 1
4 2330301 2 2 1 1 3 4 5 1 2 5 8 1 1 1 1
5 2330301 2 4 3 4 4 4 3...
2011 Apr 15
2
Function for deleting variables with >=50% missing obs from a data frame
.... For example, Q1 in one of my data frames has over 66% of its observations missing. I have tried imputation with mice but it does not work for all the data frames and I get the following message or a similar message to this:
iter imp variable
1 1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q19 Q36 Q47 Q52 Q79 Q80 Q94 Q97 Q104 Q108 Q122 Q131 Q134 P1 P2 P3 P4 P5 P6Error in solve.default(xtx + diag(pen)) :
system is computationally singular: reciprocal condition number = 1.83044e-16
In addition: Warning messages:
1: In sqrt((sum(residuals^2))/(sum(ry...
2017 May 08
0
2 patches related to silk_biquad_alt() optimization
.../* DIRECT FORM II TRANSPOSED (uses 2 element state vector) */
> opus_int k;
>
> silk_assert( ( stride == 1 ) || ( stride == 2 ) );
>
> if( stride == 1) {
> opus_int32 out32_Q14;
> for( k = 0; k < len; k++ ) {
> /* S[ 0 ], S[ 1 ]: Q12 */
> out32_Q14 = silk_LSHIFT( silk_SMLAWB( S[ 0 ], B_Q28[ 0 ], in[
> k ] ), 2 );
>
> S[ 0 ] = S[ 1 ] + silk_RSHIFT_ROUND( (opus_int64)out32_Q14 *
> (-A_Q28[ 0 ]), 30 );
> S[ 0 ] = silk_SMLAWB( S[ 0 ], B_Q28[ 1 ], in[ k ] );
>
>...
2012 Sep 21
2
[LLVMdev] RE : Question about LLVM NEON intrinsics
...1.64 {d20, d21}, [r3, :128]
add r3, r2, #48
vld1.64 {d16, d17}, [r2, :128]
add r2, r2, #16
vld1.64 {d18, d19}, [r1, :128]
vld1.64 {d26, d27}, [r12, :128]
add r12, r1, #32
vld1.64 {d24, d25}, [r3, :128]
add r1, r1, #16
vadd.f32 q11, q9, q8
vld1.64 {d28, d29}, [r12, :128]
vadd.f32 q9, q13, q12
vadd.f32 q8, q14, q10
vld1.64 {d20, d21}, [r2, :128]
vld1.64 {d24, d25}, [r1, :128]
add r1, r0, #48
vadd.f32 q10, q12, q10
vst1.64 {d22, d23}, [r0, :128]
vst1.64 {d18, d19}, [r1, :128]
add r1, r0, #32
add r0, r0, #16
vst1.64 {d16, d17}, [r1, :128]
vst1.64 {d20, d21}, [r0, :128]
bx lr
.L...
2017 May 17
0
2 patches related to silk_biquad_alt() optimization
...gt; > opus_int k;
> >
> > silk_assert( ( stride == 1 ) || ( stride == 2 ) );
> >
> > if( stride == 1) {
> > opus_int32 out32_Q14;
> > for( k = 0; k < len; k++ ) {
> > /* S[ 0 ], S[ 1 ]: Q12 */
> > out32_Q14 = silk_LSHIFT( silk_SMLAWB( S[ 0 ], B_Q28[ 0
> > ], in[ k ] ), 2 );
> >
> > S[ 0 ] = S[ 1 ] + silk_RSHIFT_ROUND(
> > (opus_int64)out32_Q14 * (-A_Q28[ 0 ]), 30 );
> > S[ 0 ] = silk_SMLAWB( S[...
2017 Apr 25
2
2 patches related to silk_biquad_alt() optimization
On Mon, Apr 24, 2017 at 5:52 PM, Jean-Marc Valin <jmvalin at jmvalin.ca> wrote:
> On 24/04/17 08:03 PM, Linfeng Zhang wrote:
> > Tested on my chromebook, when stride (channel) == 1, the optimization
> > has no gain compared with C function.
>
> You mean that the Neon code is the same speed as the C code for
> stride==1? This is not terribly surprising for an IIRC
2016 Aug 23
0
[PATCH 8/8] Optimize silk_NSQ_del_dec() for ARM NEON
...ces */
+ const opus_int16 x16[], /* I Input */
+ opus_int8 pulses[], /* O Quantized pulse signal */
+ const opus_int16 PredCoef_Q12[ 2 * MAX_LPC_ORDER ], /* I Short term prediction coefs */
+ const opus_int16 LTPCoef_Q14[ LTP_ORDER * MAX_NB_SUBFR ], /* I Long term prediction coefs */
+ const opus_int16 AR_Q13[ MAX_NB_SUBFR * MAX_SHAPE_LPC_ORDER ], /* I Noise shaping coefs...