search for: pv_cpuid

.... The attached patch explicitly disables this CPU capability inside the Linux kernel, I couldn''t measure any APERF/MPERF reads anymore with the patch applied. I am not sure if the PVOPS code is the right place to fix this, we could as well do it in the HV''s xen/arch/x86/traps.c:pv_cpuid(). Also when the Dom0 VCPUs are pinned, we could allow this, but I am not sure if it''s worth to do so. Awaiting your comments. Regards, Andre. P.S. Of course this doesn''t fix pure userland software like cpupower, but I would consider this in the user''s responsibility...

...LWP, to also adjust sub-leaf 0''s bit masks and perhaps zap output of sub-leaves > 1 when the respective bit in sub-leaf 0 is getting cleared.) Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx> --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -836,6 +836,10 @@ static void pv_cpuid(struct cpu_user_reg __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c); __clear_bit(X86_FEATURE_TOPOEXT % 32, &c); break; + case 0xd: /* XSAVE */ + if ( xsave_enabled(current) ) + break; + /* fall through */ case 5: /* MONITOR/MWAIT */...

...ct vcpu *v) Index: 2008-10-27/xen/arch/x86/traps.c =================================================================== --- 2008-10-27.orig/xen/arch/x86/traps.c 2008-10-27 11:14:44.000000000 +0100 +++ 2008-10-27/xen/arch/x86/traps.c 2008-11-19 10:16:27.000000000 +0100 @@ -754,6 +754,7 @@ static void pv_cpuid(struct cpu_user_reg __clear_bit(X86_FEATURE_XTPR % 32, &c); __clear_bit(X86_FEATURE_PDCM % 32, &c); __clear_bit(X86_FEATURE_DCA % 32, &c); + __set_bit(X86_FEATURE_HYPERVISOR % 32, &c); break; case 0x80000001: /* Modify Feature...

...n after Mukesh Dom0 series, or merged into it. --- xen/arch/x86/traps.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 940bc33..3f7a3c7 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -796,6 +796,8 @@ void pv_cpuid(struct cpu_user_regs *regs) __clear_bit(X86_FEATURE_DS, &d); __clear_bit(X86_FEATURE_ACC, &d); __clear_bit(X86_FEATURE_PBE, &d); + if ( is_pvh_vcpu(current) ) + __clear_bit(X86_FEATURE_MTRR, &d); __clear_bit(X86_FEATURE_DTES64...

...has IRQ rate limit logic, which can also help to prevent IRQ storms. Signed-off-by: Shan Haitao <haitao.shan@intel.com> changeset: 23701:7effe4eacf21 user: Keir Fraser <keir@xen.org> date: Sat Jul 16 09:09:46 2011 +0100 xen/libxc: Clean up pv_cpuid switch statements. Signed-off-by: Keir Fraser <keir@xen.org> changeset: 23700:867bb675b57b user: David Vrabel <david.vrabel@citrix.com> date: Sat Jul 16 09:05:45 2011 +0100 xen/libxc: set CPUID topology leaf as unsupported for PV guests...

...iteable); + } else + put_page_and_type(l2e_get_page(l2e)); return 0; } return 1; --- xen-unstable//./xen/arch/x86/traps.c 2008-11-04 08:22:40.000000000 -0600 +++ xen-hpage/./xen/arch/x86/traps.c 2008-11-04 08:24:35.000000000 -0600 @@ -723,7 +723,8 @@ static void pv_cpuid(struct cpu_user_reg { /* Modify Feature Information. */ __clear_bit(X86_FEATURE_VME, &d); - __clear_bit(X86_FEATURE_PSE, &d); + if (!opt_allow_hugepage) + __clear_bit(X86_FEATURE_PSE, &d); __clear_bit(X86_FEATURE_PGE, &d);...

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

There''re basically two methods to enter a given C-state: legacy (hlt + I/O read), and native(using mwait). MWAIT is always preferred when both underlying CPU and OS support, which is a more efficient way to conduct C-state transition. Xen PM relies on Dom0 to parse ACPI Cx/Px information, which involves one step to notify BIOS about a set of capabilities supported by OSPM. One capability