search for: puyan

Puyan, There is a doc on the document page which describe the list of broken GCCs. You'll need to check it once the docs are online. Rajika On Sun, Feb 21, 2010 at 11:33 AM, Puyan Lotfi <puyan at gatech.edu> wrote: > Hi > > Does there exist a list of relative compile times for sourc...

...f the Getting Started Guide, I have found: "GCC 3.4.4 (CodeSourcery ARM 2005q3-2): this compiler miscompiles LLVM when building with optimizations enabled. It appears to work with "make ENABLE_OPTIMIZED=1 OPTIMIZE_OPTION=-O1" or build a debug build." I'm trying that now. -Puyan On Sun, Feb 21, 2010 at 1:22 AM, Rajika Kumarasiri <rajika at wso2.com> wrote: > > Puyan, > There is a doc on the document page which describe the list of broken GCCs. You'll need to check it once the docs are online. > > Rajika > > On Sun, Feb 21, 2010 at 11:33 AM...

...for LLVM goes, but a lot of the docs and things on the LLVM website seem to be down this weekend. Anyways, if anyone has similar experience let me know. I dug around for some past mails on this list regarding building LLVM for this device, and all I found was something from LLVM-2.2 days. Thanks Puyan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100221/8df86000/attachment.html>

Is this the configuration you would give for an iphone? -Puyan ----- Original Message ----- From: "Jim Grosbach" <grosbach at apple.com> To: "Puyan Lotfi" <puyan at gatech.edu> Cc: llvmdev at cs.uiuc.edu Sent: Wednesday, February 17, 2010 4:42:37 PM GMT -05:00 US/Canada Eastern Subject: Re: [LLVMdev] Need help getting LLVM JIT...

...ent gcc arm (arm-linux, and also one that is arm-elf) toolchains, and have had trouble getting LLVM 2.6 to configure and compile using the --host and --build switches of the config. If there are any good guides out there on cross compiling LLVM I would be really be happy to read them. Thanks -- Puyan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100217/a9dae48e/attachment.html>

Specifying --host, --build and --target should work. For example, $ configure --host=arm-apple-darwin10 --build=i686-apple-darwin10 --target=arm-apple-darwin10 --enable-targets=arm -Jim On Feb 17, 2010, at 12:26 PM, Puyan Lotfi wrote: > Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? > I want to use the LLVM JIT on ARM for a class project this semester. > I have built and/or installed a few different gcc arm (arm-linux, and also one that is arm-elf) toolcha...

Hi, My name is Puyan and I've been exploring ways to improve the state of instruction level diffing using llvm and MIR. Below is a proposal for a new llvm tool meant to address issues encountered when diffing at the machine level. I'm eager to hear the community's feedback. Thanks PL mir-canon: A new...

...erested to know: are there are any LLVM targets in the works for Nvidia's PTX ISA? Also if anyone knows about Ocelot (a project done by some students at my school): it does the opposite of what I am trying to do (translates PTX to LLVM IR to run Cuda kernels on the CPU). Thanks in advance. -Puyan

...M pass framework offers (via the opt program) but in the JIT instead (when running lli). Is it possible to do any kind of online profiling (or optimization) of dynamically compiler code similar to writing an opt style code pass module? Or would I have to change a lot of stuff in the JIT? Thanks -Puyan

On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: > Hi > > I am interested to know: are there are any LLVM targets in the works > for Nvidia's PTX ISA? > > Also if anyone knows about Ocelot (a project done by some students at > my school): it does the opposite of what I am trying to do (translates > PTX...

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: >...

...Also, %eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. > > It's all a bikeshed, but being more consistent with assembly is probably a win. > > -- Sean Silva > > On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > Hi > > A few of us have discussed enhancing the MIR vregs to include support for named-vregs. At the moment named regs are only supported for physical registers and number regs a...

...ier to remember %/%% than $/%. Also, %eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. It's all a bikeshed, but being more consistent with assembly is probably a win. -- Sean Silva On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < llvm-dev at lists.llvm.org> wrote: > Hi > > A few of us have discussed enhancing the MIR vregs to include support for > named-vregs. At the moment named regs are only supported for physical > registers and number regs are reserved for vregs. > &gt...

Hi A few of us have discussed enhancing the MIR vregs to include support for named-vregs. At the moment named regs are only supported for physical registers and number regs are reserved for vregs. We've decided that to properly implement a syntax for MIR named vregs we first need to reorganized the sigils used for physical registers and external symbols so our proposal is to swap the sigil

...%eax and $some_symbol are already familiar from typical assembly > syntax and we probably don't want to break that association. > > It's all a bikeshed, but being more consistent with assembly is probably a > win. > > -- Sean Silva > > On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < > llvm-dev at lists.llvm.org> wrote: > >> Hi >> >> A few of us have discussed enhancing the MIR vregs to include support for >> named-vregs. At the moment named regs are only supported for physical >> registers and number regs are...

...ven optimization pass. Said process can be extremely laborious, and this is especially true when comparing shaders or compute modules. Important semantic differences are often difficult to spot because of the irregular naming and ordering of instructions. Looking for a solution we have come across Puyan Lotfi's talk at 2018 EuroLLVM on mir-canon (https://www.youtube.com/watch?v=RHT-bh_xo6U). His project inspired us to invest some time into developing a tool called llvm-canon aiming to achieve a very similar goal - a clean and obvious diff but for LLVM IR dumps. Currently the tool is used inte...

Hi, I am using visual studio 2008's generated solution file for clang/llvm. I was looking at the online demo where it gives out llvm2cpp program along with the llvm IR of the C code. I could not find any executable in the /bin directory for llvm2cpp. I was wondering if there is either source or executable of the llvm2cpp program that is used by llvm demo available for either llvm-2.7

...ask because I haven't been able to search successfully for much documentation, and I don't see the IR code when I disassemble the bitcode file. I think it is probably just part of the C runtime, but I don't know why it is showing up in the passes if it's not in the bitcode. Thanks Puyan

Hi I am trying to figure out how to link an opt pass to llvm-gcc or clang. Is there a document on how to do this? -Puyan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110120/05d5499c/attachment.html>

...would like access to a PTX backend for LLVM. :-)<br /> <br /> On Sat, Mar 27, 2010 at 6:28 PM, Ralf Karrenberg (Chareos@gmx.de) wrote:<br /> > <br /> > Hey,<br /> > <br /> > Chris Lattner schrieb: <br /> > > On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: <br /> > > <br /> > >> Hi <br /> > >> <br /> > >> I am interested to know: are there are any LLVM targets in the works <br /> > >> for Nvidia's PTX ISA? <br /> > >> <br /> > >> Al...