search for: pushq

...Note that more work is needed to both support linux/windows but I am not sure how this is best dealt with in llvm. // windows (arguments go to rcx and rdx and have reversed order)--- const uint8_t ResolverCode[] = { // resolver_entry: 0x55, // 0x00: pushq %rbp 0x48, 0x89, 0xe5, // 0x01: movq %rsp, %rbp 0x50, // 0x04: pushq %rax 0x53, // 0x05: pushq %rbx 0x51, // 0x06: pushq %rcx 0x52,...

...e how this is best dealt with in llvm. >> >> >> // windows (arguments go to rcx and rdx and have reversed order)--- >> >> const uint8_t ResolverCode[] = { >> >> // resolver_entry: >> >> 0x55, // 0x00: pushq %rbp >> >> 0x48, 0x89, 0xe5, // 0x01: movq %rsp, %rbp >> >> 0x50, // 0x04: pushq %rax >> >> 0x53, // 0x05: pushq %rbx >> >> 0x51,...

...> + * > + * Author: Joerg Roedel <jroedel at suse.de> > + */ > + > +#include <asm/segment.h> > + > +.macro EXCEPTION_HANDLER name function error_code=0 > +SYM_FUNC_START(\name) > + > + /* Build pt_regs */ > + .if \error_code == 0 > + pushq $0 > + .endif cld > + > + pushq %rdi > + pushq %rsi > + pushq %rdx > + pushq %rcx > + pushq %rax > + pushq %r8 > + pushq %r9 > + pushq %r10 > + pushq %r11 > + pushq %rbx &gt...

...86/boot/compressed/head_64.S @@ -33,6 +33,7 @@ #include <asm/processor-flags.h> #include <asm/asm-offsets.h> #include <asm/bootparam.h> +#include <asm/desc_defs.h> #include "pgtable.h" /* @@ -401,6 +402,10 @@ SYM_CODE_START(startup_64) .Lon_kernel_cs: + pushq %rsi + call load_stage1_idt + popq %rsi + /* * paging_prepare() sets up the trampoline and checks if we need to * enable 5-level paging. @@ -528,6 +533,13 @@ SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) shrq $3, %rcx rep stosq +/* + * Load stage2 IDT + */ + pushq %rsi + call load_stage2_...

...care of putting in place the intended values. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -275,15 +275,13 @@ ENTRY(sysenter_entry) pushfq .globl sysenter_eflags_saved sysenter_eflags_saved: - pushq $0 - pushq $0 + pushq $3 /* ring 3 null cs */ + pushq $0 /* null rip */ pushq $0 movl $TRAP_syscall,4(%rsp) SAVE_ALL GET_CURRENT(%rbx) cmpb $0,VCPU_sysenter_disables_events(%rbx) - movq $0,UREGS_rip(%rsp) /* null rip */ -...

...S @@ -33,6 +33,7 @@ #include <asm/processor-flags.h> #include <asm/asm-offsets.h> #include <asm/bootparam.h> +#include <asm/desc_defs.h> #include "pgtable.h" /* @@ -358,6 +359,10 @@ SYM_CODE_START(startup_64) movq %rax, gdt64+2(%rip) lgdt gdt64(%rip) + pushq %rsi + call load_stage1_idt + popq %rsi + /* * paging_prepare() sets up the trampoline and checks if we need to * enable 5-level paging. @@ -465,6 +470,16 @@ SYM_FUNC_END_ALIAS(efi_stub_entry) .text SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) +/* + * Reload GDT after relocation - The GDT...

...want to generate the compact unwind information using just the CFI directives. I *think* that this should be doable. The issue I'm facing right now is that I need to know how much the stack pointer was adjusted. So when I have something like this: .cfi_startproc Lfunc_begin175: pushq %rbp Ltmp1532: .cfi_def_cfa_offset 16 Ltmp1533: .cfi_offset %rbp, -16 movq %rsp, %rbp Ltmp1534: .cfi_def_cfa_register %rbp pushq %r15 pushq %r14 pushq %rbx subq $3224, %rsp ## imm = 0xC98 Ltmp1535: .cf...

...nction as release build do not add -debug-only option to llc executable. For the testcase sent by you earlier I have modified it as following : ;;;;; ip-regallco-simple.ll ; RUN: llc < %s | FileCheck %s -check-prefix=NOIPRA ; RUN: llc < %s -enable-ipra | FileCheck %s ; NOIPRA: foo: ; NOIPRA: pushq %r10 ; NOIPRA: pushq %r9 ; NOIPRA: pushq %r8 ; NOIPRA: callq bar1 ; CHECK: foo: ; CHECK-NOT: pushq %r10 ; CHECK-NOT: pushq %r9 ; CHECK-NOT: pushq %r8 ; CHECK: callq bar1 target triple = "x86_64-unknown-unknown" define void @bar1() { ret void } define preserve_allcc void @foo()#0 { call vo...

...* @@ -1383,10 +1388,10 @@ ENTRY(nmi) * resume the outer NMI. */ - movq $repeat_nmi, %rdx + leaq repeat_nmi(%rip), %rdx cmpq 8(%rsp), %rdx ja 1f - movq $end_repeat_nmi, %rdx + leaq end_repeat_nmi(%rip), %rdx cmpq 8(%rsp), %rdx ja nested_nmi_out 1: @@ -1440,7 +1445,8 @@ nested_nmi: pushq %rdx pushfq pushq $__KERNEL_CS - pushq $repeat_nmi + leaq repeat_nmi(%rip), %rdx + pushq %rdx /* Put stack back */ addq $(6*8), %rsp @@ -1479,7 +1485,9 @@ first_nmi: addq $8, (%rsp) /* Fix up RSP */ pushfq /* RFLAGS */ pushq $__KERNEL_CS /* CS */ - pushq $1f /* RIP */ + pushq %ra...

This set of patches converts the way frames gets created from using PUSHes/POPs to using MOVes, thus allowing (in certain cases) to avoid saving/restoring part of the register set. While the place where the (small) win from this comes from varies between CPUs, the net effect is a 1 to 2% reduction on a combined interruption entry and exit when the full state save can be avoided. 1: use MOV

One piece of code I'm writing has a lot of intermediates, and I'm trying to optimize down the number of memory accesses. Here's a snippet from the start of the function, where I think there is some low-hanging fruit: # BB#0: pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx movq %rdx, %rcx movq %rdi, -16(%rsp) # 8-byte Spill movq (%rsi), %rdi movq 8(%rsi), %r8 movq 8(%rcx), %rax movq %rax, -24(%rsp) # 8-byte Spill movq 16(%rcx), %rax movq %rax, -8(%rsp) # 8-byte Spill mo...

..._custom -std=c11 -O3 -march=native -c app2.c -S against gcc: gcc_custom -std=c11 -O3 -march=native -c app2.c -S Versions (latest for each, downloaded just a few days ago): gcc : 5.1 clang/llvm: clang+llvm-3.6.1-x86_64-apple-darwin Host: osx yosemite. The assembly (cut to the essential): LLVM: pushq %rbp movq %rsp, %rbp pushq %r14 pushq %rbx movl %edi, %r14d leal 71(%r14), %eax xorl %ecx, %ecx cmpl $56, %eax movl $92, %ebx cmovnel %ecx, %ebx leaq L_.str(%rip), %rdi callq _puts leal 71(%rbx,%r14), %eax popq %rbx popq %r14 popq %rbp retq and the gcc one: pushq %rbp mov...

...e sent by you earlier I have modified it as following : > > ;;;;; ip-regallco-simple.ll > > ; RUN: llc < %s | FileCheck %s -check-prefix=NOIPRA > > ; RUN: llc < %s -enable-ipra | FileCheck %s > > ; NOIPRA: foo: > > should be NOIPRA-LABEL: > > > ; NOIPRA: pushq %r10 > > ; NOIPRA: pushq %r9 > > ; NOIPRA: pushq %r8 > > ; NOIPRA: calls bar1 > > If this is an exact sequence you want to match, you may use NOIPRA-NEXT > > ; CHECK: foo: > > ; CHECK-NOT: pushq %r10 > > ; CHECK-NOT: pushq %r9 > >...

...s(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index bd53c57617e6..c53123468364 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -191,7 +191,7 @@ ENTRY(entry_SYSCALL_64_trampoline) * spill RDI and restore it in a second-stage trampoline. */ pushq %rdi - movq $entry_SYSCALL_64_stage2, %rdi + movabsq $entry_SYSCALL_64_stage2, %rdi JMP_NOSPEC %rdi END(entry_SYSCALL_64_trampoline) @@ -1275,7 +1275,8 @@ ENTRY(error_entry) movl %ecx, %eax /* zero extend */ cmpq %rax, RIP+8(%rsp) je .Lbstep_iret - cmpq $.Lgs_change, RIP+8(%rsp) + leaq...

...e compact unwind information using just the CFI directives. I *think* that this should be doable. The issue I'm facing right now is that I need to know how much the stack pointer was adjusted. So when I have something like this: > > .cfi_startproc > Lfunc_begin175: > pushq %rbp > Ltmp1532: > .cfi_def_cfa_offset 16 > Ltmp1533: > .cfi_offset %rbp, -16 > movq %rsp, %rbp > Ltmp1534: > .cfi_def_cfa_register %rbp > pushq %r15 > pushq %r14 > pushq %rbx > subq $3224...

...ified it as following : >> > ;;;;; ip-regallco-simple.ll >> > ; RUN: llc < %s | FileCheck %s -check-prefix=NOIPRA >> > ; RUN: llc < %s -enable-ipra | FileCheck %s >> > ; NOIPRA: foo: >> >> should be NOIPRA-LABEL: >> >> > ; NOIPRA: pushq %r10 >> > ; NOIPRA: pushq %r9 >> > ; NOIPRA: pushq %r8 >> > ; NOIPRA: calls bar1 >> >> If this is an exact sequence you want to match, you may use NOIPRA-NEXT > > >> > ; CHECK: foo: >> > ; CHECK-NOT: pushq %r10 >&gt...

...tructions .macosx_version_min 10, 12 .p2align 4, 0x90 _foo: ## @foo .cfi_startproc ## BB#0: ## InlineAsm Start movl %r14d, %r15d ## InlineAsm End retq .cfi_endproc .globl _bar .p2align 4, 0x90 _bar: ## @bar .cfi_startproc ## BB#0: pushq %r15 Ltmp0: .cfi_def_cfa_offset 16 pushq %rbx Ltmp1: .cfi_def_cfa_offset 24 pushq %rax Ltmp2: .cfi_def_cfa_offset 32 Ltmp3: .cfi_offset %rbx, -24 Ltmp4: .cfi_offset %r15, -16 ## InlineAsm Start movl %ecx, %r15d ## InlineAsm End callq _foo ## InlineAsm Start movl %r15d, %ebx ## InlineAsm End addq $8...

....section __TEXT,__text,regular,pure_instructions .globl __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE .align 4, 0x90 __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE: ## @_ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE ## BB#0: pushq %r14 pushq %rbx subq $8, %rsp movq %rsi, %rbx movq %rdi, %r14 movq %rdx, %rdi movq %rcx, %rsi callq __ZN7WebCore4viziEPKNS_20RenderBoxModelObjectEPNS_10StyleImageE movq %rax, %rcx shrq $32, %rcx testl %ecx, %ecx je LBB0_2 ## BB#1: imull (%rbx), %eax cltd idivl %ecx movl %eax, (%r14)...

...aised. 0x10002d971 <+1969>: movq -0x68(%rbp), %rdx 0x10002d975 <+1973>: movl %r13d, %ecx 0x10002d978 <+1976>: callq 0x100019720 ; sqlite3VdbeAddOp2 at sqlite3.c:37297 ... Here is lldb dis result for sqlite3VdbeAddOp3: 0x100019500 <+0>: pushq %rbp 0x100019501 <+1>: movq %rsp, %rbp 0x100019504 <+4>: pushq %r15 0x100019506 <+6>: pushq %r14 0x100019508 <+8>: pushq %r13 0x10001950a <+10>: pushq %r12 0x10001950c <+12>: pushq %rbx 0x10001950d <+13>: pushq...

...2* %2 = load i32* %1, align 4, !tbaa !0 ret i32 %2 } Note that in loadgs2, the call to toglobal has been inlined and so the back end will just see a bitcast, which SelectionDAG treats as a no-op. The assembly we get from this is: _toglobal: ## @toglobal ## BB#0: pushq %rbp movq %rsp, %rbp movq %rdi, %rax popq %rbp ret load: ## @load ## BB#0: pushq %rbp movq %rsp, %rbp movl (%rdi), %eax popq %rbp ret .globl _loadgs .align 4, 0x90 loadgs: ## @loadgs ## BB#0: pushq %rbp movq %rsp, %rbp m...