Displaying 20 results from an estimated 37 matches for "push_refn".
2015 Mar 14
1
[PATCH ddx] Add support for VRAM-less devices to the ddx
...;
bo_flags |= is_src ? NOUVEAU_BO_RD : NOUVEAU_BO_WR;
if (!nv50_style_tiled_pixmap(ppix)) {
@@ -579,7 +578,7 @@ NVC0EXAPictTexture(NVPtr pNv, PixmapPtr ppix, PicturePtr ppict, unsigned unit)
if (!nv50_style_tiled_pixmap(ppix))
NOUVEAU_FALLBACK("pixmap is scanout buffer\n");
- PUSH_REFN (push, bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+ PUSH_REFN (push, bo, NOUVEAU_BO_APER | NOUVEAU_BO_RD);
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
switch (ppict->format) {
case PICT_a8r8g8b8:
@@ -884,14 +883,14 @@ NVC0EXAPrepareComposite(int op,
PUSH_DATA (push, 0);...
2014 May 21
2
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
....c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> index 1f37527..6e68fb8 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> @@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
>
> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>
> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
> + PUSH_DATA (push, ( width << 16) | dstx);
> + PUSH_DATA (push, (height << 16) | dsty);
> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
> + PUSH_D...
2014 May 20
0
[PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...vers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index 1f37527..6e68fb8 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
+ BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, ( width << 16) | dstx);
+ PUSH_DATA (push, (height << 16) | dsty);
+ BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
+ PUSH_DATA (push, 8192 << 16);...
2014 May 21
0
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...rs/nouveau/nv50/nv50_surface.c
>> index 1f37527..6e68fb8 100644
>> --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
>> +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
>> @@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
>>
>> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>>
>> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
>> + PUSH_DATA (push, ( width << 16) | dstx);
>> + PUSH_DATA (push, (height << 16) | dsty);
>> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2...
2015 Oct 10
3
[PATCH] nv50, nvc0: don't base decisions on available pushbuf space
...*nv,
PUSH_DATA (push, bo->offset + base);
while (words) {
- unsigned nr = PUSH_AVAIL(push);
- nr = MIN2(nr, words);
- nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
+ unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN - 1);
PUSH_SPACE(push, nr + 2);
PUSH_REFN (push, bo, NOUVEAU_BO_WR | domain);
--
2.4.9
2014 May 20
14
[PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine
I went through the gallium-nine tree and picked out nouveau patches that are
general bug-fixes. The first bunch I'd like to also get into 10.2. I've
reviewed all of them and they make sense to me, but sending them out for
public review as well in case there are any objections.
Unless I hear objections, I'd like to push this by Friday.
Christoph Bumiller (11):
nv50,nvc0: always pull
2014 Nov 19
5
[PATCH v2 0/3] nouveau: support for custom VRAM domains
This series is to allow NVIDIA chips with shared memory to operate more
efficiently (and to operate at all once we disable VRAM from the kernel
driver) by allowing nouveau_screen to specify a domain to use for objects
originally allocated into VRAM. If the domain is not overridden, the default
NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be
used in place of
2014 May 27
1
[PATCH V3] nvc0: implement clear_buffer
...O: Find a way to do this with the GPU! */
+ nvc0_clear_buffer_cpu(pipe, res, offset, size, data, data_size);
+ return;
+ }
+
+ elements = size / data_size;
+
+ height = (elements + 16383) / 16384;
+
+ width = elements / height;
+
+ if (!PUSH_SPACE(push, 40))
+ return;
+
+ PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
+
+ BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
+ PUSH_DATAf(push, color.f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+...
2014 May 26
1
[PATCH V2] nvc0: implement clear_buffer
...d a way to do this with the GPU!
+ nvc0_clear_buffer_cpu(pipe,res,offset,size,data,data_size);
+ }
+ else {
+
+ elements = size / data_size;
+
+ height = (elements + 16383) / 16384;
+
+ width = elements / height;
+
+ if (!PUSH_SPACE(push, 40))
+ return;
+
+ PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
+
+ BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
+ PUSH_DATAf(push, color.f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISS...
2014 Nov 19
0
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...;< 20) - 0x100);
- ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
+ ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
&screen->uniform_bo);
if (ret)
goto fail;
- PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
for (i = 0; i < 5; ++i) {
/* TIC and TSC entries for each unit (nve4+ only) */
@@ -898,7 +898,7 @@ nvc0_screen_create(st...
2016 Jun 05
0
[RFC PATCH] nouveau: add locking
...[1]);
PUSH_DATAf(push, color->f[2]);
PUSH_DATAf(push, color->f[3]);
- if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
+ if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0)) {
+ pipe_mutex_unlock(nv50->screen->base.push_mutex);
return;
+ }
PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
@@ -353,6 +362,8 @@ nv50_clear_render_target(struct pipe_context *pipe,
BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
PUSH_DATA (push, nv50->cond_condmode);
+ pipe_mutex_unlock(nv50->screen->base.push_mutex);
+
nv50->dirty_3d |...
2015 Oct 10
2
[PATCH] nv50, nvc0: don't base decisions on available pushbuf space
...while (words) {
>> - unsigned nr = PUSH_AVAIL(push);
>> - nr = MIN2(nr, words);
>> - nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
>> + unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN - 1);
>> PUSH_SPACE(push, nr + 2);
>> PUSH_REFN (push, bo, NOUVEAU_BO_WR | domain);
>
>
2014 Nov 19
1
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...uveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
> + ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
> &screen->uniform_bo);
> if (ret)
> goto fail;
>
> - PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
> + PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
>
> for (i = 0; i < 5; ++i) {
> /* TIC and TSC entries for each unit (nve4+ only) */
> @@ -898,7 +89...
2014 May 26
2
Implement buffer_clear for nvc0
Hi, please review the following patch!
Thanks,
Tobias Klausmann
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...R_C2, A_C3, 8_8_8_8));
> PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
> PUSH_DATA (push, NV50TSC_1_0_WRAPS_REPEAT |
> NV50TSC_1_0_WRAPT_REPEAT |
> @@ -651,16 +645,8 @@ NVC0EXAPictTexture(NVPtr pNv, PixmapPtr ppix, PicturePtr ppict, unsigned unit)
>
> PUSH_REFN (push, bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
> PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
> - PUSH_DATA (push, format);
> - PUSH_DATA (push, bo->offset);
> - PUSH_DATA (push, (bo->offset >> 32) |
> - (bo->config.nvc0.tile_mode << 18) |
&...
2014 Nov 19
1
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...t = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
> + ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
> &screen->uniform_bo);
> if (ret)
> goto fail;
>
> - PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
> + PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
>
> for (i = 0; i < 5; ++i) {
> /* TIC and TSC entries for each unit (nve4+ only) */
> @@ -898,7 +898,7 @...
2014 May 26
0
[PATCH] nvc0: Implement buffer_clear for this type of hardware
...ed element size");
+ return;
+ }
+
+ assert(size % data_size == 0);
+
+ if (data_size != 12) {
+
+ elements = size / data_size;
+
+ height = (elements + 16383) / 16384;
+
+ width = elements / height;
+
+ if (!PUSH_SPACE(push, 40))
+ return;
+
+ PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
+
+ BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
+ PUSH_DATAf(push, color.f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISS...
2014 Oct 27
4
[PATCH 0/3] nouveau: support for custom VRAM domains
This series is to allow NVIDIA chips with shared memory to operate more
efficiently (and to operate at all once we disable VRAM from the kernel
driver) by allowing nouveau_screen to specify a domain to use for objects
originally allocated into VRAM. If the domain is not overridden, the default
NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be
used in place of
2014 Oct 21
0
[PATCH v2] nv50: Handle ARB_conditional_render_inverted and enable it
...H_DATA (push, cond);
return;
}
- q = nv50_query(pq);
- if (mode == PIPE_RENDER_COND_WAIT ||
- mode == PIPE_RENDER_COND_BY_REGION_WAIT) {
+ if (wait) {
BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
PUSH_DATA (push, 0);
}
+ PUSH_SPACE(push, 8);
+ PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
BEGIN_NV04(push, NV50_3D(COND_ADDRESS_HIGH), 3);
PUSH_DATAh(push, q->bo->offset + q->offset);
PUSH_DATA (push, q->bo->offset + q->offset);
- PUSH_DATA (push, NV50_3D_COND_MODE_RES_NON_ZERO);
+ PUSH_DATA (push, cond...
2015 Jun 19
5
[PATCH v3 0/2] nouveau: support for custom VRAM domains
New revision of this patchset that prevents VRAM objects from being
allocated on VRAM-less systems like Tegra. This is required for Mesa
to work on such systems.
Changes since v2:
- Use vram_size to detect systems without VRAM and set the correct
domain instead of expecting each chip to set its domain explicitly.
Alexandre Courbot (2):
nouveau: support for custom VRAM domains
nvc0: use