Displaying 12 results from an estimated 12 matches for "pty_fd".
2013 Aug 08
1
[PATCH v2 7/7] Sample Implementation of Intel MIC User Space Daemon.
...s_buf[0]) },
> + { .iov_base = vcons_buf[1], .iov_len = sizeof(vcons_buf[1]) },
> + };
> + struct iovec *iov0 = &vcons_iov[0], *iov1 = &vcons_iov[1];
> + struct mic_info *mic = (struct mic_info *)arg;
> + int err;
> + struct pollfd console_poll[MAX_CONSOLE_FD];
> + int pty_fd;
> + char *pts_name;
> + ssize_t len;
> + struct mic_vring tx_vr, rx_vr;
> + struct mic_copy_desc copy;
> + struct mic_device_desc *desc;
> +
> + pty_fd = posix_openpt(O_RDWR);
> + if (pty_fd < 0) {
> + mpsslog("can't open a pseudoterminal master device: %s\n...
2013 Aug 08
1
[PATCH v2 7/7] Sample Implementation of Intel MIC User Space Daemon.
...s_buf[0]) },
> + { .iov_base = vcons_buf[1], .iov_len = sizeof(vcons_buf[1]) },
> + };
> + struct iovec *iov0 = &vcons_iov[0], *iov1 = &vcons_iov[1];
> + struct mic_info *mic = (struct mic_info *)arg;
> + int err;
> + struct pollfd console_poll[MAX_CONSOLE_FD];
> + int pty_fd;
> + char *pts_name;
> + ssize_t len;
> + struct mic_vring tx_vr, rx_vr;
> + struct mic_copy_desc copy;
> + struct mic_device_desc *desc;
> +
> + pty_fd = posix_openpt(O_RDWR);
> + if (pty_fd < 0) {
> + mpsslog("can't open a pseudoterminal master device: %s\n...
2013 Aug 08
0
[PATCH v2 7/7] Sample Implementation of Intel MIC User Space Daemon.
...cons_buf[0], .iov_len = sizeof(vcons_buf[0]) },
+ { .iov_base = vcons_buf[1], .iov_len = sizeof(vcons_buf[1]) },
+ };
+ struct iovec *iov0 = &vcons_iov[0], *iov1 = &vcons_iov[1];
+ struct mic_info *mic = (struct mic_info *)arg;
+ int err;
+ struct pollfd console_poll[MAX_CONSOLE_FD];
+ int pty_fd;
+ char *pts_name;
+ ssize_t len;
+ struct mic_vring tx_vr, rx_vr;
+ struct mic_copy_desc copy;
+ struct mic_device_desc *desc;
+
+ pty_fd = posix_openpt(O_RDWR);
+ if (pty_fd < 0) {
+ mpsslog("can't open a pseudoterminal master device: %s\n",
+ strerror(errno));
+ goto _return...
2004 Apr 14
1
PPTP Server running behind Shorewall
...trol Message (type: 7)
Apr 13 19:28:32 FWONP pptpd[3118]: CTRL: 0 min_bps, 1525 max_bps, 32 window size
Apr 13 19:28:32 FWONP pptpd[3118]: CTRL: Made a OUT CALL RPLY packet
Apr 13 19:28:32 FWONP pptpd[3118]: CTRL: Starting call (launching pppd, opening
GRE)
Apr 13 19:28:32 FWONP pptpd[3118]: CTRL: pty_fd = 5
Apr 13 19:28:32 FWONP pptpd[3118]: CTRL: tty_fd = 6
Apr 13 19:28:32 FWONP pptpd[3119]: CTRL (PPPD Launcher): Connection speed =
115200
Apr 13 19:28:32 FWONP pptpd[3119]: CTRL (PPPD Launcher): local address =
10.200.10.2
Apr 13 19:28:32 FWONP pptpd[3119]: CTRL (PPPD Launcher): remote address =...
2013 Aug 08
10
[PATCH v2 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v1 => v2:
a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring
into 3 smaller patches and function renames, as per feedback from
Greg Kroah-Hartman.
b) Use VRINGH infrastructure for accessing virtio rings from the host
in patch 5, as per feedback from Michael S. Tsirkin.
v1: Initial post @ https://lkml.org/lkml/2013/7/24/810
Description:
2013 Aug 08
10
[PATCH v2 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v1 => v2:
a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring
into 3 smaller patches and function renames, as per feedback from
Greg Kroah-Hartman.
b) Use VRINGH infrastructure for accessing virtio rings from the host
in patch 5, as per feedback from Michael S. Tsirkin.
v1: Initial post @ https://lkml.org/lkml/2013/7/24/810
Description:
2013 Aug 21
10
[PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v2 => v3:
a) Patch 1 data structure cleanups, header file include cleanups,
IDA interface reuse and switching to device_create_with_groups(..)
as per feedback from Greg Kroah-Hartman.
b) Patch 7 signal documentation, sleep workaround removal and sysfs
access API cleanups as per feedback from Michael S. Tsirkin.
v1 => v2: @ http://lwn.net/Articles/563131/
a)
2013 Aug 21
10
[PATCH v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v2 => v3:
a) Patch 1 data structure cleanups, header file include cleanups,
IDA interface reuse and switching to device_create_with_groups(..)
as per feedback from Greg Kroah-Hartman.
b) Patch 7 signal documentation, sleep workaround removal and sysfs
access API cleanups as per feedback from Michael S. Tsirkin.
v1 => v2: @ http://lwn.net/Articles/563131/
a)
2013 Sep 05
16
[PATCH RESEND v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v2 => v3:
a) Patch 1 data structure cleanups, header file include cleanups,
IDA interface reuse and switching to device_create_with_groups(..)
as per feedback from Greg Kroah-Hartman.
b) Patch 7 signal documentation, sleep workaround removal and sysfs
access API cleanups as per feedback from Michael S. Tsirkin.
v1 => v2: @ http://lwn.net/Articles/563131/
a)
2013 Sep 05
16
[PATCH RESEND v3 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v2 => v3:
a) Patch 1 data structure cleanups, header file include cleanups,
IDA interface reuse and switching to device_create_with_groups(..)
as per feedback from Greg Kroah-Hartman.
b) Patch 7 signal documentation, sleep workaround removal and sysfs
access API cleanups as per feedback from Michael S. Tsirkin.
v1 => v2: @ http://lwn.net/Articles/563131/
a)
2013 Jul 25
16
[PATCH 0/5] Enable Drivers for Intel MIC X100 Coprocessors.
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after
2013 Jul 25
16
[PATCH 0/5] Enable Drivers for Intel MIC X100 Coprocessors.
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after