search for: ptrvt

...// Calculate and remember argument location. + else + CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, + TailCallArguments); + ... - // We are emitting Altivec params in order. - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, - DAG.getConstant(ArgOffset, PtrVT)); - SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); - MemOpChains.push_back(Store); + if (!isTailCall) { + // We are emitting Altivec params in order. + PtrOff = DAG.getNode...

...ion. > + else > + CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, > ArgOffset, > + TailCallArguments); > + > ... > - // We are emitting Altivec params in order. > - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, > - DAG.getConstant(ArgOffset, PtrVT)); > - SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); > - MemOpChains.push_back(Store); > + if (!isTailCall) { > + // We are emitting Altivec params in order. &...

Hello Dale, this is an updated version of the tail call optimization patch for powerpc. could you have a look at it? i added code to support ppc64 (untested, will try to get access to ppc64 on a friend's machine). incorporated evan's formatting suggestions. ;) will run another round of testing (llvm-test) on my powerpc g4/800 when i get the okay to commit. testing on this machine takes

...argetLowering::getValueType() doesn't work for arbitrary address spaces, you should fix it. I think my earlier comments about getIntPtrConstant still hold: instead of "DAG.getIntPtrConstant(Offset, addrSpace)", you can just write "DAG.getConstant(Offset, PtrTy)". + EVT NewPtrVT = TLI.getPointerTy(dyn_cast<PointerType>( + SV->getType())->getAddressSpace()); + if (PtrVT != NewPtrVT) { + // Check to see if we want to change the size of the pointer + // based on the address space and if so extend or truncate the pointer. + Ptr = DAG.getSExtOrTrunc...

...orContents(ZeroOrNegativeOneBooleanContent); @@ -2050,6 +2050,90 @@ AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op, } } +SDValue +AArch64TargetLowering::LowerGlobalAddressDarwin(SDValue Op, + SelectionDAG &DAG) const { + + EVT PtrVT = getPointerTy(); + SDLoc dl(Op); + const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op); + const GlobalValue *GV = GN->getGlobal(); + unsigned Alignment = GV->getAlignment(); + Reloc::Model RelocM = getTargetMachine().getRelocationModel(); + if (GV->isWeakForLinker()...

...lse >> + CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, >> ArgOffset, >> + TailCallArguments); >> + >> ... >> - // We are emitting Altivec params in order. >> - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, >> - DAG.getConstant(ArgOffset, PtrVT)); >> - SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); >> - MemOpChains.push_back(Store); >> + if (!isTailCall) { >> + // We are emitting Altivec par...

Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions have something similar... MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MemOp[0] = cast<MemSD...

...Dr. ERDI Gergo via llvm-dev wrote: > Hi, > > During instruction selection, I have the following code for certain > LOAD instructions: > > const LoadSDNode *LD = cast<LoadSDNode>(N); > SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), > VT, PtrVT, MVT::Other, > LD->getBasePtr(), LD->getChain()); > > // Honestly, I have no idea what this does, but other memory > // accessing instructions have something similar... > MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); >...

> -----Original Message----- > From: Villmow, Micah > Sent: Friday, August 24, 2012 2:56 PM > To: 'Eli Friedman' > Cc: LLVM Developers Mailing List > Subject: RE: [LLVMdev] RFC: Supporting different sized address space > arithmetic > > Eli, > There is a patch that implements the beginning what I think is the > correct approach to support the backend

Hi, Is it possible to add a spill code (a pair of store /load ) to the machinecode in a pass before the instruction emitter? If so, how can I calculate the address (offset to the sp) for the spill store/load instructions? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

The reason the ones in PPCInstrInfo.td don't have the patterns to match is the reason they are more analogous to your problem. Namely, tblgen does not have a way to produce nodes with more than one result. The load-with-update instructions do exactly that - one of the inputs is also an output, but the other output is independent (and necessarily a separate register). The FMA variants have

...'t work for arbitrary address > spaces, you should fix it. > > I think my earlier comments about getIntPtrConstant still hold: > instead of "DAG.getIntPtrConstant(Offset, addrSpace)", you can just > write "DAG.getConstant(Offset, PtrTy)". > > + EVT NewPtrVT = TLI.getPointerTy(dyn_cast<PointerType>( > + SV->getType())->getAddressSpace()); > + if (PtrVT != NewPtrVT) { > + // Check to see if we want to change the size of the pointer > + // based on the address space and if so extend or truncate the > pointer. >...

On Tue, 30 May 2017, Nemanja Ivanovic wrote: > This is typically accomplished with something like PPC's `RegConstraint` and > `NoEncode`. You can see examples of it that are very similar to what you're after in > PPC's load/store with update forms (i.e. load a value and update the base register > with the effective address - these are used for pre-increment loads/stores).

...the return type of "__trampoline_setup" (whatever that is) and that didn't change. > false, false, false, false, 0, CallingConv::C, false, > /*isReturnValueUsed=*/true, > DAG.getExternalSymbol("__trampoline_setup", PtrVT), > Args, DAG, dl); > > - SDValue Ops[] = > - { CallResult.first, CallResult.second }; > - > - return DAG.getMergeValues(Ops, 2, dl); > + return CallResult.second; > } > --- a/lib/Transforms/InstCombine/InstCombineCalls.cpp > +++ b/lib/Transfor...

Hi! Attached set of patches splits llvm.init.trampoline into an "init" phase and an "adjust" phase, as discussed on the "Go on dragonegg" thread. Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Split-intrinsics-and-DAG-nodes.patch Type: text/x-diff Size: 8808 bytes Desc:

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...>getOperand(1), - Node->getOperand(2), dl); - SplitVectorOp(Tmp, Lo, Hi); - break; - } - case ISD::VECTOR_SHUFFLE: { - // Build the low part. - SDValue Mask = Node->getOperand(2); - SmallVector<SDValue, 8> Ops; - MVT PtrVT = TLI.getPointerTy(); - - // Insert all of the elements from the input that are needed. We use - // buildvector of extractelement here because the input vectors will have - // to be legalized, so this makes the code simpler. - for (unsigned i = 0; i != NewNumElts_Lo; ++i) { - SDVa...