search for: ptr_rc

Hi all, I've been poking at AsmParser support for powerpc64 (ppc64-elf-linux-abi) and have run into some behavior I don't understand with the ptr_rc references coming out of the PPC*.td files when generating the asm-matcher files. For instance : $ ./build/bin/llvm-tblgen llvm/lib/Target/PowerPC/PPC.td -I ~/llvm-head/llvm/include -I ~/llvm-head/llvm/lib/Target/PowerPC/ -gen-asm-matcher <...> Included from llvm/lib/Target/PowerPC/PPC.t...

On Fri, 2012-09-14 at 13:10 -0500, Will Schmidt wrote: > Hi all, > > I've been poking at AsmParser support for powerpc64 > (ppc64-elf-linux-abi) and have run into some behavior I don't understand > with the ptr_rc references coming out of the PPC*.td files when > generating the asm-matcher files. > > For instance : > $ ./build/bin/llvm-tblgen llvm/lib/Target/PowerPC/PPC.td -I > ~/llvm-head/llvm/include -I ~/llvm-head/llvm/lib/Target/PowerPC/ > -gen-asm-matcher > > <...> >...

...t; pattern> Instruction { let Namespce = "MyNameSpace"; MyOpCode myop = op; MySubOpcode mysubop = subop; dag OutOprandList = outs; dag InOprandList = ins; let ASMString = asmstr; let Pattern = pattern; } def My_ADDINST1: MyInst <MYADD1, NO_SUBOP, (outs ptr_rc: $dest), (ins: $ptr_rc:$ptr1, Int32RC:$src) "myadd1 $dst, $ptr1, $src1", [(set $ptr_rc:$dst,(add $ptr_rc:ptr1, Int32RC:$src))]>; it is giving me error like impossible to select. Could anybody help me resolve this issue. Any example would be highly appreciated.

...9 at 18:41 -0500, Will Schmidt wrote: > On Fri, 2012-09-14 at 13:10 -0500, Will Schmidt wrote: > > Hi all, > > > > I've been poking at AsmParser support for powerpc64 > > (ppc64-elf-linux-abi) and have run into some behavior I don't understand > > with the ptr_rc references coming out of the PPC*.td files when > > generating the asm-matcher files. > > > > For instance : > > $ ./build/bin/llvm-tblgen llvm/lib/Target/PowerPC/PPC.td -I > > ~/llvm-head/llvm/include -I ~/llvm-head/llvm/lib/Target/PowerPC/ > > -gen-asm-match...

On Nov 15, 2012, at 2:54 PM, Will Schmidt <will_schmidt at vnet.ibm.com> wrote: > > Can anyone confirm or deny tablegen supporting PointerLikeRegClass? X86 is using it. You could start by determining what PPC is doing differently. /jakob

What does MIOperandInfo exactly mean while defining an Operand class? e.g. here class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); } -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20071204/23db1ace/attachment.html>

...o my Sparc back-end. 1) I defined a new register call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I added method addPointerRegClass() to my InstrInfo class The compiler generates the some code as before, but that seems to be ok, because I haven't used ptr_rc yet. 4) I changed the address mode MEMri: def MEMri : Operand<iPTR> { let PrintMethod = "printMemOperand"; // was: let MIOperandInfo = (ops IntRegs, i32imm); let MIOperandInfo = (ops ptr_rc, i32imm); } for the C code int c; void f(void) { c = 4711; } I get the error me...

...m"; } class LD_D_DESC : LD_DESC_BASE<"ldvd", load, v32i16, MSA128DOpnd>; I've tried to change mem_msa to hold only let MIOperandInfo = (ops simm10) but there are problems it seems: // MSA specific address operand def mem_msa : mem_generic { let MIOperandInfo = (ops ptr_rc, simm10); let EncoderMethod = "getMSAMemEncoding"; } Could you please tell me what is the simplest way to define in LD_DESC_BASE a $addrsrc that is just an immediate value like i16 or i16imm? Thank you very much, Alex

...: error: expected memory with 32-bit signed offset         gslbx           $2,0($3,$4)                                       ^ I just copy-n-paste  mem_generic  and  getMemEncoding: def gs_mem : Operand<iPTR> {   let PrintMethod = "printMemOperand";   let MIOperandInfo = (ops ptr_rc, ptr_rc, simm16); ^-- for two registers   let EncoderMethod = "getGSMemEncoding";                                             ^-- just encoding two registers and one offset   let ParserMatchClass = MipsMemAsmOperand;   let OperandType = "OPERAND_MEMORY"; } ----- 8< --...

...1) I defined a new register call AddrRegs > 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) > 3) I added method addPointerRegClass() to my InstrInfo class > > The compiler generates the some code as before, but that seems to > be ok, because I haven't used ptr_rc yet. > > 4) I changed the address mode MEMri: > > def MEMri : Operand<iPTR> { > let PrintMethod = "printMemOperand"; > // was: let MIOperandInfo = (ops IntRegs, i32imm); > let MIOperandInfo = (ops ptr_rc, i32imm); > } > > for the C code int c;...

...has been selected as data register instructions). Returning the data register class generates a bunch of illegal moves, such as move.l 8(d0), d1. Here, d0 has to be an address register. The root cause of this is instructions that get emitted with the M_LOOK_UP_PTR_REG_CLASS flag, because I have a ptr_rc in my address mode selection patterns for loads and stores. Also, I'm uncertain as to how this custom DR->AR op replacer pass fits into this whole soup and where it is supposed to happen, as I'm still pretty clueless with llvm internals. :) Thanks, Andreas

On Sep 24, 2007, at 1:12 AM, Andreas Fredriksson wrote: > On 9/24/07, Evan Cheng <evan.cheng at apple.com> wrote: > >> I am going to suggest something shocking. :) Since you will end up >> writing a >> bunch of target specific code anyway, you might a well write a target >> specific pass that change generic instructions into data register >> variant

...t;"ldvd", load, v32i16, MSA128DOpnd>; > > > I've tried to change mem_msa to hold only let MIOperandInfo = (ops > simm10) but there > are problems it seems: > > // MSA specific address operand > def mem_msa : mem_generic { > let MIOperandInfo = (ops ptr_rc, simm10); > let EncoderMethod = "getMSAMemEncoding"; > } > > > > Could you please tell me what is the simplest way to define in > LD_DESC_BASE a $addrsrc > that is just an immediate value like i16 or i16imm? > > Thank you very much, > Alex...

...ta register instructions). > > Returning the data register class generates a bunch of illegal moves, > such as move.l 8(d0), d1. Here, d0 has to be an address register. The > root cause of this is instructions that get emitted with the > M_LOOK_UP_PTR_REG_CLASS flag, because I have a ptr_rc in my address > mode selection patterns for loads and stores. I think it should return DR register class. My theory is if all the nodes are already fixed right after selection, scheduling and allocation should just work. > > > Also, I'm uncertain as to how this custom DR->A...