search for: ptes

...he pages in the address range may not be migrating. In this case, the non migrating pages won't have a new GPU MMU entry to store but the nvif_object_ioctl() NVIF_VMM_V0_PFNMAP method doesn't check the input and stores a bad valid GPU page table entry. Fix this by skipping the invalid input PTEs when updating the GPU page tables. Signed-off-by: Ralph Campbell <rcampbell at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c b/drivers/gp...

...he pages in the address range may not be migrating. In this case, the non migrating pages won't have a new GPU MMU entry to store but the nvif_object_ioctl() NVIF_VMM_V0_PFNMAP method doesn't check the input and stores a bad valid GPU page table entry. Fix this by skipping the invalid input PTEs when updating the GPU page tables. Signed-off-by: Ralph Campbell <rcampbell at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c b/drivers/gp...

...he pages in the address range may not be migrating. In this case, the non migrating pages won't have a new GPU MMU entry to store but the nvif_object_ioctl() NVIF_VMM_V0_PFNMAP method doesn't check the input and stores a bad valid GPU page table entry. Fix this by skipping the invalid input PTEs when updating the GPU page tables. Signed-off-by: Ralph Campbell <rcampbell at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c b/drivers/gp...

The patch deals with the situation which guest OS uses unused page table pages as data pages and write data to them. The pages will still be grabbed by Xen as page table pages, and lots of unnecessary page faults occur. The patch will check if the data guest writes to the page table contains valid mfn or not, if not, we believe it is a data page now and then unshadow the page. The patch

...dev/mmu/vmmgp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c @@ -258,12 +258,94 @@ gp100_vmm_pd0_unmap(struct nvkm_vmm *vmm, VMM_FO128(pt, vmm, pdei * 0x10, 0ULL, 0ULL, pdes); } +static void +gp100_vmm_pd0_pfn_unmap(struct nvkm_vmm *vmm, + struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes) +{ + struct device *dev = vmm->mmu->subdev.device->dev; + dma_addr_t addr; + + nvkm_kmap(pt->memory); + while (ptes--) { + u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 0); + u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 4); + u64 data = (u64)da...

hi, what''s the best way (if at all) to iterate through all of a domain''s page tables within xen 2.0.6? i need to find all references to a specific pte value (which is a given). essentially, a reverse page-table lookup. i''m hesitant to switch to 3.0, but if it''s easier to do what i want, just let me know. thanks, -A. -- Aaron Marks Distributed Systems Lab

...rio Faggioli <dario.faggioli@citrix.com> Date: Tue Sep 10 19:54:20 2013 +0200 tools/misc: introduce xen-mfndump. A little development and debugging tool, useful when looking for information about MFN to PFN mappings, MFN/PFN mappings in a guest''s PTEs, etc. This is what it can do as of now: $ /usr/sbin/xen-mfndump Usage: xen-mfndump <command> [args] Commands: help show this help dump-m2p show M2P dump-p2m <domid> show P2M of &...

...to hand. > > Whatever triggers the __builtin_memcpy() paths, and even the size==8 > paths on 32bit. > > You could put a WARN in there to easily find them. There were several cases that I found during writing the *ONCE stuff. For example there are some 32bit ppc variants with 64bit PTEs. Some for others (I think sparc). And the mm/ code is perfectly fine with these PTE accesses being done NOT atomic. > > The advantage of introducing the SINGLE_{LOAD,STORE}() helpers is that > they compiletime validate this the size is 'right' and can runtime check > alignmen...

...to hand. > > Whatever triggers the __builtin_memcpy() paths, and even the size==8 > paths on 32bit. > > You could put a WARN in there to easily find them. There were several cases that I found during writing the *ONCE stuff. For example there are some 32bit ppc variants with 64bit PTEs. Some for others (I think sparc). And the mm/ code is perfectly fine with these PTE accesses being done NOT atomic. > > The advantage of introducing the SINGLE_{LOAD,STORE}() helpers is that > they compiletime validate this the size is 'right' and can runtime check > alignmen...

...the memory backed mappings are >> unmapped, but the VKBuffer isn't de-allocated, and hence sparse >> mappings need to be re-deployed? >> >> Let's assume the sparse VKBuffer (and hence the VA space allocation) >> is pretty large. In Nouveau the corresponding PTEs would have a >> rather huge page size to cover this. Now, if small memory backed >> mappings are mapped to this huge sparse buffer, in Nouveau we'd >> allocate a new PT with a corresponding smaller page size overlaying >> the sparse mappings PTEs. >> >> H...

...mapped on a sparse range? What happens when the memory backed mappings are unmapped, but the VKBuffer isn't de-allocated, and hence sparse mappings need to be re-deployed? Let's assume the sparse VKBuffer (and hence the VA space allocation) is pretty large. In Nouveau the corresponding PTEs would have a rather huge page size to cover this. Now, if small memory backed mappings are mapped to this huge sparse buffer, in Nouveau we'd allocate a new PT with a corresponding smaller page size overlaying the sparse mappings PTEs. How would this look like in amdgpu? > > When yo...

Hi, On paravirt x86 (both 32- and 64-bit), since cset 13998: http://xenbits.xensource.com/xen-unstable.hg?rev/13998 we translate all ptes from being mfn-based to pfn-based when the hardware _PAGE_PRESENT bit is cleared. We do this for PROT_NONE pages, which appear to the HV to be non-present, but which are special-cased in the kernel to appear present (a different bit in the pte remains set for these pages and is caught by the pte_p...

...) mode it dynamically maintains a list of intervals. ODP chooses the align the dynamic intervals to it's HW page table levels, and not to SW VMAs. This is much simpler to manage and faster to fault, at the cost of capturing more VA for invalidations which have to be probed against the HW shadow PTEs. > It isn't that expensive, there is an extra driver lock/unlock as > part of the lookup and possibly a find_vma() and kmalloc(GFP_ATOMIC) > for new intervals. Also, the deferred interval updates for munmap(). > Compared to the cost of updating PTEs in the device and GPU fault >...

At OLS I gave a talk on some of the Xen scalability inhibitors, and one of these was writable page tables. We went over why the feature does not scale, but just as important, we found that the uniprocessor case does not provide any advantage either. These tests were done on x86_64, so I wanted to run the 1-way test on 32 bit to show the same problem. So, I have run with writable PTs and

The goal for this series is to introduce the hmm_pfn_to_map_order() function. This allows a device driver to know that a given 4K PFN is actually mapped by the CPU using a larger sized CPU page table entry and therefore the device driver can safely map system memory using larger device MMU PTEs. The series is based on 5.8.0-rc3 and is intended for Jason Gunthorpe's hmm tree. These were originally part of a larger series: https://lore.kernel.org/linux-mm/20200619215649.32297-1-rcampbell at nvidia.com/ Changes in v3: Replaced the HMM_PFN_P[MU]D flags with hmm_pfn_to_map_order() to indi...

When thinking about multithreading the device model, it occurred to me that it''s a little odd that we''re doing a memcmp to determine which portions of the VRAM has changed. Couldn''t we just use dirty page tracking in the shadow paging code? That should significantly lower the overhead of this plus I believe the infrastructure is already mostly there in the shadow2

...enough memory to allocate the pte pages needed to cover the fixmap virtual memory range, minus the single page allocated by head_32.S; - account for the page already allocated by early_ioremap_init; - account for the two additional pages that might be needed to make sure that the kmap''s ptes are contiguous. Unfortunately this code is rather complex and depends on the behaviour of other functions but I hope to have covered all the corner cases. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> R...

The ptep_establish macro is only used on user-level PTEs, for P->P mapping changes. Since these always happen under protection of the pagetable lock, the strong synchronization of a 64-bit cmpxchg is not needed, in fact, not even a lock prefix needs to be used. We can simply instead clear the P-bit, followed by a normal set. The write ordering is s...

...ys_pmd_init(pmd_t *pmd, unsigned long address, unsigned long end) @@ -648,9 +670,9 @@ void __init extend_init_mapping(unsigned } } -static void __init find_early_table_space(unsigned long end) +static unsigned long __init find_early_table_space(unsigned long end) { - unsigned long puds, pmds, ptes, tables; + unsigned long puds, pmds, ptes, tables, fixmap_tables; puds = (end + PUD_SIZE - 1) >> PUD_SHIFT; pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT; @@ -660,7 +682,16 @@ static void __init find_early_table_spac round_up(pmds * 8, PAGE_SIZE) + round_up(ptes * 8, PAGE_SIZE)...

Hi, 2.6.29-rc3 x86_64 guest on x86_64 RHEL5.3 host: https://bugzilla.redhat.com/484295 kernel BUG at mm/filemap.c:123! invalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC last sysfs file: /sys/devices/vbd-51712/block/xvda/xvda2/dev CPU 0 Modules linked in: ipv6 xts lrw gf128mul sha256_generic cbc dm_crypt