search for: pt_pci_host_read

The OpRegion shouldn''t be mapped 1:1 because the address in the host can''t be used in the guest directly. This patch traps read and write access to the opregion of the Intel GPU config space (offset 0xfc). To work correctly this patch needs a change in hvmloader. HVMloader will allocate 2 pages for the OpRegion and write this address on the config space of the Intel GPU. Qemu

...ics.c index c6f8869..7302b25 100644 --- a/hw/pt-graphics.c +++ b/hw/pt-graphics.c @@ -3,6 +3,7 @@ */ #include "pass-through.h" +#include "pci.h" #include "pci/header.h" #include "pci/pci.h" @@ -40,9 +41,11 @@ void intel_pch_init(PCIBus *bus) did = pt_pci_host_read(pci_dev_1f, PCI_DEVICE_ID, 2); rid = pt_pci_host_read(pci_dev_1f, PCI_REVISION, 1); - if ( vid == PCI_VENDOR_ID_INTEL ) - pci_bridge_init(bus, PCI_DEVFN(0x1f, 0), vid, did, rid, - pch_map_irq, "intel_bridge_1f"); + if (vid == PCI_VENDOR_ID_INTEL)...

This series contains all the fixes required to produce a working IGD passthrough box. All the changes are previously seen in the dev list but not yet accepted. Some of them are out-dated and need some reshape. Detailed description can be found later in each patch. . [PATCH 1/3] qemu-xen-trad/pt_msi_disable: do not clear all MSI flags . [PATCH 2/3] qemu-xen-trad: Correctly expose PCH ISA bridge

...ruct pt_dev *pci_dev) void igd_write_opregion(struct pt_dev *real_dev, uint32_t val) { uint32_t host_opregion = 0; + uint32_t map_size = 2; int ret; if ( igd_guest_opregion ) @@ -74,11 +93,13 @@ void igd_write_opregion(struct pt_dev *real_dev, uint32_t val) host_opregion = pt_pci_host_read(real_dev->pci_dev, PCI_INTEL_OPREGION, 4); igd_guest_opregion = (val & ~0xfff) | (host_opregion & 0xfff); PT_LOG("Map OpRegion: %x -> %x\n", host_opregion, igd_guest_opregion); + //If the opregion is not page-aligned, map one more page to fit the entire region....