search for: psxldq_imm

...6 imm:$imm)), (LO16 imm:$imm))>; > > It is possible to write multi-instruction pattern, e.g. > X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? > Sounds like you want to define them as SDNodeXform that returns upper > and lower 16 bits respectively. Take a look at PSxLDQ_imm in > X86InstrSSE.td as an example. Another good example is the PPC backend, which has the exact same issue for integer constants. >> - The return instruction for Cell SPU is "bi $lr". How do I jam that >> into the instruction info w/o tblgen bitching up a storm about t...

Chris Lattner wrote: >>It is possible to write multi-instruction pattern, e.g. >>X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>Sounds like you want to define them as SDNodeXform that returns upper >>and lower 16 bits respectively. Take a look at PSxLDQ_imm in >>X86InstrSSE.td as an example. > > > Another good example is the PPC backend, which has the exact same issue > for integer constants. Actually, for SPU, not quite the same: def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val), "ilhu $rT...

...(IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>; It is possible to write multi-instruction pattern, e.g. X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? Sounds like you want to define them as SDNodeXform that returns upper and lower 16 bits respectively. Take a look at PSxLDQ_imm in X86InstrSSE.td as an example. > > - The return instruction for Cell SPU is "bi $lr". How do I jam that > into the instruction info w/o tblgen bitching up a storm about the > "$" or the extra "bi" operands? I am not sure. Does "bi \$lr"...

I was able to resolve my previous question about dealing with custom loads/stores, and following Chris' suggestion, the IBM Cell SPU backend can generate code for "int main(void) { return 0; }" without crashing llc. There's a lot of work still to be done... like getting frame offsets correctly computed and hauling in the raft of intrinsics that the Cell SDK defines. Three quick

...t;> It is possible to write multi-instruction pattern, e.g. >>> X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>> Sounds like you want to define them as SDNodeXform that returns >>> upper >>> and lower 16 bits respectively. Take a look at PSxLDQ_imm in >>> X86InstrSSE.td as an example. >> >> >> Another good example is the PPC backend, which has the exact same >> issue >> for integer constants. > > Actually, for SPU, not quite the same: > > def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u...