Displaying 6 results from an estimated 6 matches for "pseudoi".
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pseudo
2018 Feb 01
1
Intrinsic pattern matching
...t with "llvm.x86.".
def int_x86_mpx_bndmk:
Intrinsic<[llvm_x86bnd_ty], [llvm_ptr_ty, llvm_i64_ty], []>;
}
```
And following instruction that is generated when @llvm.x86.mpx.bndmk is
used in code:
```
let isPseudo = 1 in
let usesCustomInserter = 1 in
def BNDMK64rm_Int: PseudoI<(outs BNDR:$dst), (ins i64mem:$src,
GR64:$shift),
[(set BNDR:$dst, (int_x86_mpx_bndmk addr:$src, i64:$shift))]>;
```
Everything works completely fine, intrinsic gets matched. But if I add
"IntrNoMem" attribute to instrinsic like:
```
let TargetPrefix = "x86" in { // A...
2015 Apr 28
2
[LLVMdev] Lowering intrinsic that return an int1
...c in "Intrinsics.td":
_def int_antivm : Intrinsic<[llvm_i1_ty], [], [], "llvm.antivm">;_
Then I want to lower it in the X86 backend, so I defined a pseudo
instruction in "X86InstrCompiler.td":
_let usesCustomInserter = 1, Defs = [EFLAGS] in {_
_def ANTIVM : PseudoI<(outs), (ins), [(int_antivm)]>;_
_}_
I wrote my custom inserter:
_MachineBasicBlock *_
_X86TargetLowering::EmitANTIVMWithCustomInserter(_
_ MachineInstr *MI,_
_ MachineBasicBlock *MBB) const {_
_ // Some stuff, _
_ MI->eraseFromParent(); // The pseudo is gone now._
_ return BB;_
_}_...
2015 Oct 22
2
add intrinsic function support for customized backend
Hi, All,
I want to add one intrinsic function for my particular backend. Let's say
the intrinsic function is named "foo" which takes two i32 inputs and has
one i32 output.
First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in
/include/llvm/IR/Intrinsics.td.
Then, in my target/InstrInfo.td, I'm supposed
2015 Oct 22
2
add intrinsic function support for customized backend
...32.i32(i32, i32)*
*******************************************************************************************
In InstroInfo.td, I define a pseudo instruction like this :
******************************************************************************************
*let isPseudo = 1 in {*
* def FOO : MyPseudoInst<(outs GRRegs:$dst) , (ins GRRegs:$src1,
GRRegs:$src2),*
* "foo $dst, $src1, $src2",*
* [(set i32:$dst, (int_foo i32:$src1, i32:$src2))]> {*
* }*
*} *
***************************************************************************************...
2018 Mar 28
0
x86 instruction format which takes a single 64-bit immediate
...isplacement
hasEVEX_RC - Indicates that EVEX.L'L should be used for embedded rounding control
hasNoTrackPrefix - Instruction has notrack prefix. Should only occur on indirect calls and jumps.
The X86Inst class should not be used directly to define any instruction. Instructions should use PseudoI, I, Ii8, Ii8Reg, Ii8PCRecl, Ii16, Ii32, Ii32S, FPI, FPI_, Iseg16, or Iseg32 classes. Or a subclass of one of those. These classes take care of setting the ImmT field correctly. All of the I* classes take Opcode and Form as an argument. The remaining fields have defaults that can be overridden via m...
2018 Mar 28
4
x86 instruction format which takes a single 64-bit immediate
I am attempting to create an instruction which takes a single 64-bit
immediate. This doesn't seem like a thing that would exist already (because
who needs an instruction which just takes an immediate?) How might I
implement this easily? Perhaps I could use a format which encodes a
register, which is then unused?
Thanks for the help.
Gus
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