search for: promotenod

Displaying 8 results from an estimated 8 matches for "promotenod".

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2012 Mar 23
2
[LLVMdev] Fixing VAARG on PPC64
...work > > because SDValue DAGTypeLegalizer::PromoteIntRes_VAARG seems to have > > the appropriate logic. Is this a bug, or am I misunderstanding how > > Promote works? > > IMHO, you are doing it right but it looks like ISD::VAARG is not > handled in SelectionDAGLegalize::PromoteNode() yet. DAGTypeLegalizer > is used to legalize "non-legal" types regardless of the operation > (need confirmation). Thanks! That makes sense, and looking more closely at the PromoteIntRes_VAARG code, it finds the type to which to promote by calling TLI.getRegisterType, which won...
2012 Mar 23
0
[LLVMdev] Fixing VAARG on PPC64
...gt;> because SDValue DAGTypeLegalizer::PromoteIntRes_VAARG seems to have >>> the appropriate logic. Is this a bug, or am I misunderstanding how >>> Promote works? >> IMHO, you are doing it right but it looks like ISD::VAARG is not >> handled in SelectionDAGLegalize::PromoteNode() yet. DAGTypeLegalizer >> is used to legalize "non-legal" types regardless of the operation >> (need confirmation). > Thanks! That makes sense, and looking more closely at the > PromoteIntRes_VAARG code, it finds the type to which to promote by > calling TLI.getRegi...
2015 Feb 05
8
[LLVMdev] type legalization/operation action
Dear there, I have a target which is supporting the 32 bit operations natively. Right now,I want to make it support the 16 bits operations as well. My initial thought is: (1) I can adding something like “ CCIfType< [i16], CCPromoteToType<i32>>”, to the CallingConv.td, then “all” the 16 bits operands will be automatically promoted to 32 bits, it will be all set. but looks it is not
2009 Dec 22
2
[LLVMdev] LegalizeDAG Error?
The LegalizeDAG.cpp file has this code in SelectionDAGLegalize::PromoteNode: case ISD::BSWAP: { unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, DAG.getConstant(DiffBits, TLI...
2009 Dec 22
0
[LLVMdev] LegalizeDAG Error?
On Dec 22, 2009, at 2:38 PMPST, Bill Wendling wrote: > The LegalizeDAG.cpp file has this code in > SelectionDAGLegalize::PromoteNode: > > case ISD::BSWAP: { > unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); > Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); > Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); > Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, > D...
2012 Mar 23
0
[LLVMdev] Fixing VAARG on PPC64
...effect. I thought this would work > because SDValue DAGTypeLegalizer::PromoteIntRes_VAARG seems to have the > appropriate logic. Is this a bug, or am I misunderstanding how Promote > works? IMHO, you are doing it right but it looks like ISD::VAARG is not handled in SelectionDAGLegalize::PromoteNode() yet. DAGTypeLegalizer is used to legalize "non-legal" types regardless of the operation (need confirmation). Ivan > > Thanks again, > Hal >
2012 Mar 23
2
[LLVMdev] Fixing VAARG on PPC64
The PowerPC backend on PPC64 for non-Darwin (SVR4 ABI) systems currently has a problem handling integer types smaller than 64 bits. This is because the ABI specifies that these types are zero-extended to 64 bits on the stack and the default logic provided in LegalizeDAG does not use that convention. Specifically, for these targets we have: setOperationAction(ISD::VAARG, MVT::Other, Expand);
2012 Jun 04
3
[LLVMdev] Predicate registers/condition codes question
On Sun, Jun 3, 2012 at 7:11 AM, Ivan Llopard <ivanllopard at gmail.com> wrote: >> So the solution that I was investigating looks like this: >> >>      for (unsigned int i = 0; i<  ISD::BUILTIN_OP_END; ++i) { >>        switch (i) { >>        // By default all operations on i8 have to be promoted to i32. >>        default: >>