Displaying 5 results from an estimated 5 matches for "promoteintbinop".
2012 May 23
2
[LLVMdev] Predicate registers/condition codes question
...egal on i8?
>
> I think the combo TargetLowerInfo::isTypeDesirableForOp() and
> IsDesirableToPromoteOp() may help you here. X86 does something similar.
I just tried these functions, and it seems like they are only
modifying the behavior of type promotions for a small subset of
operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
PromoteLoad, SimplifyBinOpWithSameOpcodeHands, visitSRL, visitTRUNCATE
that matter to the performance of i16 on X86.)
I don't like the "desirable" in the name of these functions: in the
case of Hexagon it is illegal to use an i8 predicate register f...
2012 May 24
0
[LLVMdev] Predicate registers/condition codes question
...think the combo TargetLowerInfo::isTypeDesirableForOp() and
>> IsDesirableToPromoteOp() may help you here. X86 does something similar.
>
> I just tried these functions, and it seems like they are only
> modifying the behavior of type promotions for a small subset of
> operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
> PromoteLoad, SimplifyBinOpWithSameOpcodeHands, visitSRL, visitTRUNCATE
> that matter to the performance of i16 on X86.)
>
> I don't like the "desirable" in the name of these functions: in the
> case of Hexagon it is illegal to use an...
2012 May 22
0
[LLVMdev] Predicate registers/condition codes question
Hi Sebastian,
On 22/05/2012 23:25, Sebastian Pop wrote:
> Hi Eli,
>
> On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman<eli.friedman at gmail.com> wrote:
>> On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum<tlinth at codeaurora.org> wrote:
>>> Hey folks,
>>>
>>> We are having some difficulty with how we have been representing our
>>>
2012 May 22
2
[LLVMdev] Predicate registers/condition codes question
Hi Eli,
On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote:
>> Hey folks,
>>
>> We are having some difficulty with how we have been representing our
>> predicate registers, and wanted some advice from the list. First, we
>> had been
2012 May 24
3
[LLVMdev] Predicate registers/condition codes question
...eDesirableForOp() and
> >> IsDesirableToPromoteOp() may help you here. X86 does something
> >> similar.
> >
> > I just tried these functions, and it seems like they are only
> > modifying the behavior of type promotions for a small subset of
> > operations (PromoteIntBinOp, PromoteIntShiftOp, PromoteExtend,
> > PromoteLoad, SimplifyBinOpWithSameOpcodeHands, visitSRL,
> > visitTRUNCATE that matter to the performance of i16 on X86.)
> >
> > I don't like the "desirable" in the name of these functions: in the
> > case of Hexago...