search for: procresource

...erybody, I'm reading the .td files defining the Cortex-A57 processor, which is a subtarget of AArch64 target, and there is something confusing me in the `AArch64SchedA57.td` file. In the top of `AArch64SchedA57.td`, various processor resource are defined, as follows ``` def A57UnitB : ProcResource<1>; // Type B micro-ops def A57UnitI : ProcResource<2>; // Type I micro-ops def A57UnitM : ProcResource<1>; // Type M micro-ops def A57UnitL : ProcResource<1>; // Type L micro-ops def A57UnitS : ProcResource<1>; // Type S micro-ops def A57UnitX : ProcResource...

...ve been unable to solve this problem. Does anyone have any idea what I might be doing wrong? Here are my resource definitions from lib/Target/R600/SISchedule.td // BufferSize = 0 means the processors are in-order. let BufferSize = 0 in { // XXX: Are the resource counts correct? def HWBranch : ProcResource<1>; def HWExport : ProcResource<7>; // Taken from S_WAITCNT def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT def HWSALU : ProcResource<1>; def HWVMEM : ProcResource<15>; // Taken from S_WAITCNT def HWVALU : ProcResource<1>; } Thanks, Tom

...anks, Tom > Andy > > > Here are my resource definitions from lib/Target/R600/SISchedule.td > > > > // BufferSize = 0 means the processors are in-order. > > let BufferSize = 0 in { > > > > // XXX: Are the resource counts correct? > > def HWBranch : ProcResource<1>; > > def HWExport : ProcResource<7>; // Taken from S_WAITCNT > > def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT > > def HWSALU : ProcResource<1>; > > def HWVMEM : ProcResource<15>; // Taken from S_WAITCNT > > def H...

We have a two different dimensions for each instruction: slot assignments, and operand timings. These two are unrelated to each other, and also each (or both) can change for any given instruction from one architecture version to the next. The main concern for us was which of these mechanisms contains all the information that we need. We cannot express all the scheduling details by hand, and

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has 256 registers, but there is a significant performance penalty if you use more than a certain amount. Do any of the MachineSchedulers support switching into an 'optimize for register pressure...

Hi Krzysztof, 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org>: > > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using

...ng on defining a SchedMachineModel for the Southern Islands > family of GPUs, and I have two questions related to the > MachineScheduler. > > 1. I have a resource that can process 15 instructions at the same time. > In the TableGen definitions, should I do: > > def HWVMEM : ProcResource<15>; > or > > let BufferSize = 15 in { > def HWVMEM : ProcResource<1>; > } For in-order processors you always want BufferSize=0. In the current generic scheduler (ConvergingScheduler) it's effectively a boolean that specifies inorder vs OOO. (I have code that models...

...No. The machine model is used to form a scheduling DAG independent of the original schedule. If it's important to be this precise, then I suggest you plugin a new MachineSchedStrategy where you can model stalls for any special cases during scheduling. You need a super-resource: def P5600A : ProcResource<2>; def P5600AGQ : ProcResource<1> { let Super = P5600A; } def P5600ALQ : ProcResource<1> { let Super = P5600A; } I'll take a look at MachineSchedStrategy. I don't know how important that precision is likely to be at the moment but I've generally found that the more a...

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

Hi Andy, I'm working on defining new machine model for my target, But I don't understand how to define the in-order machine (reservation tables) in new model. For example, if target has IF ID EX WB stages should I do: let BufferSize=0 in { def IF: ProcResource<1>; def ID: ProcResource<1>; def EX: ProcResource<1>; def WB: ProcResource<1>; } def : WriteRes<WriteALU, [IF, ID, EX1, WB]> ; or define each stage as SchedWrite type and use WriteSequence to define this sequence? Thanks, Kuan-Hsu 2013/10/16 Andrew Trick <atrick...

...riteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST: InstrItinClass; def ALU1: ProcResource<1>; def ALU2: ProcResource<1>; def WriteALU1: SchedWriteRes<[ALU1]> { let Latency = 1; } def WriteALU2: SchedWriteRes<[ALU2]> { let Latency = 2; } def : ItinRW<[WriteALU1, WriteALU2], [II_TEST]> From this example, we can access the latency information of MI with &...

...n llvm support this kind of constraint? Thank you, Nick Johnson D. E. Shaw Research // Excerpted from lib/Target/MyTarget/MyTargetSchedule.td: // def DesGCv3GenericModel : SchedMachineModel { let IssueWidth = 1; let MicroOpBufferSize = 0; let CompleteModel = 1; } // ... def FlexU : ProcResource<64> { let BufferSize = 1; } def : WriteRes<IIFlexRead, [FlexU]> { let Latency = 25; let ResourceCycles = [25]; } class SchedFlexRead : Sched< [IIFlexRead] >; // I apply this to the definition of FXLV instruction // ...

...; let MispredictPenalty = 16; // This flag is set to allow the scheduler to assign a default model to // unrecognized opcodes. let CompleteModel = 0; } def WriteALU : SchedWrite; def WriteBranch : SchedWrite; let SchedModel = MyTargetModel in { // SLOT0 can handles everything def Slot0 : ProcResource<1>; // SLOT1 can't handles branches def Slot1 : ProcResource<1>; // Many micro-ops are capable of issuing on multiple ports. def SlotAny : ProcResGroup<[Slot0, Slot1]>; def : WriteRes<WriteALU, [SlotAny]> { let Latency = 1; let ResourceCycles =[1]; } def : WriteR...

On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine model. > it's make sense, but there is the another problem, the scheduled code is badly. > > load/store instruction always reuse the same register I filed PR17593 with this information. However, I

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =

[I tweaked the subject, #262824 did not introduce the problem, it is just the version I am first seeing this problem] A quick update - I have added 'Sched<[]>' as a base class for all instructions, and also: let hasNoSchedulingInfo = 1; to all the Pseudos, but while most of the errors have gone, I still get the diagnostic for 'COPY' thus: error : No schedule

...ad.html#92849> [ subject ] <http://lists.llvm.org/pipermail/llvm-dev/2015-November/subject.html#92849> [ author ] <http://lists.llvm.org/pipermail/llvm-dev/2015-November/author.html#92849> ------------------------------ Hi all, I am working on a backend that uses the ProcResource scheduling model and one limitation I found is that while it is possible to specify multiple SchedWrites in a ReadAdvance record, each write uses the same cycle count. I tried writing multiple ReadAdvance records for the same SchedRead, but tablegen does not seem to allow that. It would be useful...

I am, of course, a huge fan of this effort. :) > >> >> - >> >> [??] Make the tool work for other CPUs. This mainly depends on the >> presence of performance counters. >> >> Having these requirements documented will be great. In particular, it's important to document what kind of functionality we need out of the PMU rather than any

...<http://lists.llvm.org/pipermail/llvm-dev/2015-November/subject.html#92849> > [ author ] > <http://lists.llvm.org/pipermail/llvm-dev/2015-November/author.html#92849> > > ------------------------------ > > Hi all, > > I am working on a backend that uses the ProcResource scheduling model > and one limitation I found is that while it is possible to specify > multiple SchedWrites in a ReadAdvance record, each write uses the same > cycle count. I tried writing multiple ReadAdvance records for the same > SchedRead, but tablegen does not seem to allow that....

...ail/llvm-dev/2015-November/subject.html#92849> >> [ author ] >> <http://lists.llvm.org/pipermail/llvm-dev/2015-November/author.html#92849> >> >> ------------------------------ >> >> Hi all, >> >> I am working on a backend that uses the ProcResource scheduling model >> and one limitation I found is that while it is possible to specify >> multiple SchedWrites in a ReadAdvance record, each write uses the same >> cycle count. I tried writing multiple ReadAdvance records for the same >> SchedRead, but tablegen does not seem...