search for: procresgroup

...ops def A57UnitL : ProcResource<1>; // Type L micro-ops def A57UnitS : ProcResource<1>; // Type S micro-ops def A57UnitX : ProcResource<1>; // Type X micro-ops def A57UnitW : ProcResource<1>; // Type W micro-ops let SchedModel = CortexA57Model in { def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops } ``` According the Cortex-A57 software optimization manual, Cortex-A57 has 8 function units in the backend, - Branch(B) - Integer 0(I0) - Integer 1(I1) - Integer Muti-Cycle(M) - Load(L) - Store(S) - FP/ASIMD 0(F0) - FP/ASIMD 1(F1)...

...expect at the moment. I'm not sure I fully understand the super-resource suggestion. I've attached my WIP so you can take a look at the code in context but the relevant extracts are below. def P5600IssueALU : ProcResource<1>; def P5600IssueAL2 : ProcResource<1>; def P5600ALQ : ProcResGroup<[P5600IssueALU]> { let BufferSize = 16; } def P5600AGQ : ProcResGroup<[P5600IssueAL2, ...]> { let BufferSize = 16; } def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>; def P5600WriteAL2 : SchedWriteRes<[P5600IssueAL2]>; def P5600WriteEitherALU : SchedWriteVariant< [S...

Hi, I’m trying to work out the behavior of llvm-mca on instructions with ProcResGroups. My current understanding is: When an instruction requests a port group (e.g., HWPort015) and all of its atomic sub-resources (e.g., HWPort0,HWPort1,HWPort5), HWPort015 is marked as “reserved” and is issued in parallel with HWPort0, HWPort1, and HWPort5, blocking future instructions from reservin...

We have a two different dimensions for each instruction: slot assignments, and operand timings. These two are unrelated to each other, and also each (or both) can change for any given instruction from one architecture version to the next. The main concern for us was which of these mechanisms contains all the information that we need. We cannot express all the scheduling details by hand, and

> On May 9, 2020, at 5:12 PM, Andrea Di Biagio via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > The llvm scheduling model is quite simple and doesn't allow mca to accurately simulate the execution of individual uOPs. That limitation is sort-of acceptable if you consider how the scheduling model framework was originally designed with a different goal in mind (i.e. machine

Hi Krzysztof, 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org>: > > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using

Hi Alex, On Sun, May 10, 2020 at 4:00 PM Alex Renda <renda at csail.mit.edu> wrote: > Thanks, that’s very helpful! > > > > Also, sorry for the miscue on that bug with the 2/4 cycles — I realize now > that that’s an artifact of a change that I made to not crash when resource > groups overlap without all atomic subunits being specified: > > `echo 'fxrstor

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

...eALU : SchedWrite; def WriteBranch : SchedWrite; let SchedModel = MyTargetModel in { // SLOT0 can handles everything def Slot0 : ProcResource<1>; // SLOT1 can't handles branches def Slot1 : ProcResource<1>; // Many micro-ops are capable of issuing on multiple ports. def SlotAny : ProcResGroup<[Slot0, Slot1]>; def : WriteRes<WriteALU, [SlotAny]> { let Latency = 1; let ResourceCycles =[1]; } def : WriteRes<WriteBranch, [Slot0]> { let Latency = 1; let ResourceCycles =[1]; } } I've also changed OR1K.td to have def : ProcessorModel<"generic", My...