Displaying 5 results from an estimated 5 matches for "processor_techdocs".
2012 Mar 23
7
LWP Interrupt Handler
I am adding interrupt support for LWP, whose spec is available at
http://support.amd.com/us/Processor_TechDocs/43724.pdf. Basically OS can
specify an interrupt vector in LWP_CFG MSR; the interrupt will be
triggered when event buffer overflows. For HVM guests, I want to
re-inject this interrupt back into the guest VM. Here is one idea
similar to virtualized PMU: It first registers a special interrupt
ha...
2010 May 04
0
[PATCH] svm: support EFER.LMSLE for guests
Now that the feature is officially documented (see
http://support.amd.com/us/Processor_TechDocs/24593.pdf), I think it
makes sense to also allow HVM guests to make use of it.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Andre Przywara <andre.przywara@amd.com>
--- 2010-05-04.orig/xen/arch/x86/hvm/hvm.c 2010-04-22 14:43:25.000000000 +0200
+++ 2010-05-04/xen/arch/x86/hvm/hv...
2013 Apr 16
0
Re: XSA-36 / howto fix broken IVRS ACPI table
...>
> > However, they need details about what to fix, which I don''t know either.
> >
> > Could you pls. give me some hints which I can forward to the manufacturer
> > support?
>
> They should look at AMD IOMMU spec. For example,
> support.amd.com/us/Processor_TechDocs/48882.pdf. Tables 77 and 79.
>
> More specifically, the problem is these two entries:
>
> (XEN) AMD-Vi: IVHD Device Entry: type 0x48 id 0x0 flags 0xd7
> (XEN) AMD-Vi: IVHD Special: 0000:00:14.0 variety 0x1 handle 0x8
> ..
> (XEN) AMD-Vi: IVHD Device Entry: type 0x48 id 0...
2013 Mar 12
5
XSA-36 / howto fix broken IVRS ACPI table
Hello,
since applying the patches related to XSA-36 Xen recognizes a broken IVRS ACPI
table and disables I/O virtualisation.
I contacted the manufacturer of the mainboard/BIOS and they want to help me by
providing a patched BIOS - so far so good.
However, they need details about what to fix, which I don''t know either.
Could you pls. give me some hints which I can forward to the
2011 Nov 18
5
[PATCH 0 of 4] amd iommu: IOMMUv2 support
...ew features advertised by iommu
extended feature register. It introduces guest level IO translation and
supports state-of-the-art ATS/ATC devices with demand paging capability.
Please refer to AMD IOMMU Architectural Specification [1] for more details.
Thanks,
Wei
[1] http://support.amd.com/us/Processor_TechDocs/48882.pdf
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