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On 11/11/2017 12:44 PM, Amara Emerson wrote: > >> On Nov 10, 2017, at 10:04 PM, Aditya Nandakumar <proaditya at gmail.com >> <mailto:proaditya at gmail.com>> wrote: >>> >>> The current DAGCombine, being constructed on top of SDAG, has a kind >>> of built-in CSE and automatic DCE. How will things change, if >>> they'll change, in this new model? &gt...

...case of failure. You can use -global-isel-abort=2 option. llc -global-isel -pass-remarks-missed="gisel-*" -global-isel-abort=2 simple_foo.ll Regards, Igor From: S. Bharadwaj Yadavalli [mailto:bharadwajy at gmail.com] Sent: Thursday, November 09, 2017 03:36 To: Aditya Nandakumar <proaditya at gmail.com> Cc: Craig Topper <craig.topper at gmail.com>; llvm-dev <llvm-dev at lists.llvm.org>; Breger, Igor <igor.breger at intel.com> Subject: Re: [llvm-dev] [GlobalISel] [X86] unable to legalize instruction Sorry for the late follow-up. Here is the output with the sugge...

> On Nov 11, 2017, at 11:03 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > On 11/11/2017 12:44 PM, Amara Emerson wrote: >> >>> On Nov 10, 2017, at 10:04 PM, Aditya Nandakumar <proaditya at gmail.com <mailto:proaditya at gmail.com>> wrote: >>>> >>>> The current DAGCombine, being constructed on top of SDAG, has a kind of built-in CSE and automatic DCE. How will things change, if they'll change, in this new model? >>> Hi Hal, >>&gt...

I believe if you pass(iirc) -pass-remarks-missed=“gisel-*”, it’ll print the instruction it failed to legalize. Sent from my iPhone > On Oct 11, 2017, at 6:44 PM, S. Bharadwaj Yadavalli via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Thanks for your quick reply. > > Here its is: > > =========== > > ; ModuleID = 'simple_foo.c' > source_filename

> On Nov 10, 2017, at 10:19 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > On 11/10/2017 11:12 AM, Amara Emerson via llvm-dev wrote: >> Hi everyone, >> >> This RFC concerns the design and architecture of a generic machine instruction combiner/optimizer framework to be developed as part of the GISel pipeline. As we transition from

Hi I am new to the LLVM infrastructure. I would like to contribute to the project. Looking at all the information available on LLVM, I am a little overwhelmed. I have taken a compiler design course and have worked on another compiler project. I was wondering if anyone could suggest a little roadmap where I can get my feet wet a little. I am currently not sure where to start. I know this is not

Thanks for your quick reply. Here its is: =========== ; ModuleID = 'simple_foo.c' source_filename = "simple_foo.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.13.0" ; Function Attrs: noinline nounwind optnone ssp uwtable define i32 @foo(i32 %a, i32 %b, i32 %c) #0 { entry: %retval = alloca i32, align