Displaying 5 results from an estimated 5 matches for "printregisterlist".
2010 Mar 19
2
[LLVMdev] Instruction with variable number of outputs
Hi,
After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like:
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
let PrintMethod = "printRegisterList";
}
def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeNone, LdStMulFrm, IIC_iLoadm,
"ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
Tablegen produces an instruc...
2010 Mar 19
0
[LLVMdev] Instruction with variable number of outputs
...i,
>
> After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like:
>
> // A list of registers separated by comma. Used by load/store multiple.
> def reglist : Operand<i32> {
> let PrintMethod = "printRegisterList";
> }
>
> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
> reglist:$dsts, variable_ops),
> IndexModeNone, LdStMulFrm, IIC_iLoadm,
> "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
&g...
2010 Mar 19
2
[LLVMdev] Instruction with variable number of outputs
...fter Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like:
>>
>> // A list of registers separated by comma. Used by load/store multiple.
>> def reglist : Operand<i32> {
>> let PrintMethod = "printRegisterList";
>> }
>>
>> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
>> reglist:$dsts, variable_ops),
>> IndexModeNone, LdStMulFrm, IIC_iLoadm,
>> "ldm${addr:submode}${p}\t$addr, $dsts", &qu...
2010 Mar 22
0
[LLVMdev] Instruction with variable number of outputs
...ts. The following operands are fine as they fall in the variable_ops part of the instruction.
>
> I need a way of referring to the variable_ops by name without forcing the first operand to be an input.
Ok.
>>> def reglist : Operand<i32> {
>>> let PrintMethod = "printRegisterList";
>>> let MIOperandInfo = (ops variable_ops);
>>> }
>>>
>>> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts),
>
> This syntax is not ideal, because reglist:$dsts is a variable list of output operands. But at least there is no...
2017 Jan 13
2
NDS32 V3 backend
Hi all,
On behalf of Andes Technology Corp,
I am proposing a backend targeting the NDS32 V3 ISA.
NDS32 V3 ISA is a 16/32 bit mixed instruction set architecture that
developed By AndesTech.
You can find more information at the Andes website <http://www.andestech.com/>,
and reference AndeStar ISA Manual (V3 ISA) from document download page
<http://www.andestech.com/product.php?cls=9>.