Displaying 17 results from an estimated 17 matches for "printinst".
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2013 Jun 25
2
[LLVMdev] Auxiliary operand types for disassembler.
...number of insns inside the packet.
In order for the disassembler to correctly represent the insn it needs
to accumulate the series of insns that form the packet. Only when the
entire packet is known can the meaning of the parse bits be properly
interpreted.
Changing objdump's interface to printInst so it passes the raw insn bits
down would allow the printer to accumulate the same information and
would work just as well I think.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
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2015 Jul 28
2
[LLVMdev] Wrong encoding/decoding for POPC instruction of Sparc
...0x00000001096a5811 __assert_rtn + 81
7 llvm-mc 0x000000010963f4e8
llvm::SparcInstPrinter::printOperand(llvm::MCInst const*, int,
llvm::MCSubtargetInfo const&, llvm::raw_ostream&) + 136
8 llvm-mc 0x000000010963eae0
llvm::SparcInstPrinter::printInstruction(llvm::MCInst const*,
llvm::MCSubtargetInfo const&, llvm::raw_ostream&) + 256
9 llvm-mc 0x000000010964f5e6
llvm::SparcInstPrinter::printInst(llvm::MCInst const*, llvm::raw_ostream&,
llvm::StringRef, llvm::MCSubtargetInfo const&) + 86
10 llvm-mc...
2015 Jul 31
2
[LLVMdev] Wrong encoding/decoding for POPC instruction of Sparc
..._rtn + 81
>> 7 llvm-mc 0x000000010963f4e8
>> llvm::SparcInstPrinter::printOperand(llvm::MCInst const*, int,
>> llvm::MCSubtargetInfo const&, llvm::raw_ostream&) + 136
>> 8 llvm-mc 0x000000010963eae0
>> llvm::SparcInstPrinter::printInstruction(llvm::MCInst const*,
>> llvm::MCSubtargetInfo const&, llvm::raw_ostream&) + 256
>> 9 llvm-mc 0x000000010964f5e6
>> llvm::SparcInstPrinter::printInst(llvm::MCInst const*, llvm::raw_ostream&,
>> llvm::StringRef, llvm::MCSubtargetInfo const&...
2015 Jul 31
0
[LLVMdev] Wrong encoding/decoding for POPC instruction of Sparc
...001096a5811 __assert_rtn + 81
> 7 llvm-mc 0x000000010963f4e8
> llvm::SparcInstPrinter::printOperand(llvm::MCInst const*, int,
> llvm::MCSubtargetInfo const&, llvm::raw_ostream&) + 136
> 8 llvm-mc 0x000000010963eae0
> llvm::SparcInstPrinter::printInstruction(llvm::MCInst const*,
> llvm::MCSubtargetInfo const&, llvm::raw_ostream&) + 256
> 9 llvm-mc 0x000000010964f5e6
> llvm::SparcInstPrinter::printInst(llvm::MCInst const*, llvm::raw_ostream&,
> llvm::StringRef, llvm::MCSubtargetInfo const&) + 86
>...
2013 Jun 25
0
[LLVMdev] Auxiliary operand types for disassembler.
...r of insns inside the packet. In order for the disassembler to correctly represent the insn it needs to accumulate the series of insns that form the packet. Only when the entire packet is known can the meaning of the parse bits be properly interpreted.
>
> Changing objdump's interface to printInst so it passes the raw insn bits down would allow the printer to accumulate the same information and would work just as well I think.
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
> <MCInst.h.diff>_______________________...
2011 Oct 13
0
[LLVMdev] llvm-objdump related patch
...uint64_t addr;
- if (error(i->getAddress(addr))) break;
- outs() << format("%8x:\t", addr + Index);
- DumpBytes(StringRef(Bytes.data() + Index, Size));
+ DumpBytes(StringRef(Bytes.data() + Index - SectionVMA, Size));
IP->printInst(&Inst, outs(), "");
outs() << "\n";
} else {
errs() << ToolName << ": warning: invalid instruction encoding\n";
if (Size == 0)
- Size = 1; // skip illegible bytes
+ Size = 4; // skip...
2011 Jun 22
0
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
...tches.
In meantime I wrote a patch which changes to old mnemonics for shift instructions.
This fixes compiling on the freebsd.
--- a/contrib/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/contrib/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -44,17 +44,18 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
const MCOperand &MO2 = MI->getOperand(2);
const MCOperand &MO3 = MI->getOperand(3);
- O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
+ O << '\t' << "mov&quo...
2011 Oct 12
2
[LLVMdev] llvm-objdump related patch
Michael,
I have rework the patch according to your suggestion. And I have
read binutil/objdump source code and found that it has a logic that if
there's no symtab, it will use dynsym, which is missing in llvm-objdump.
Songmao
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2015 Jul 31
1
[LLVMdev] Wrong encoding/decoding for POPC instruction of Sparc
...t; 7 llvm-mc 0x000000010963f4e8
>>> llvm::SparcInstPrinter::printOperand(llvm::MCInst const*, int,
>>> llvm::MCSubtargetInfo const&, llvm::raw_ostream&) + 136
>>> 8 llvm-mc 0x000000010963eae0
>>> llvm::SparcInstPrinter::printInstruction(llvm::MCInst const*,
>>> llvm::MCSubtargetInfo const&, llvm::raw_ostream&) + 256
>>> 9 llvm-mc 0x000000010964f5e6
>>> llvm::SparcInstPrinter::printInst(llvm::MCInst const*, llvm::raw_ostream&,
>>> llvm::StringRef, llvm::MCSubt...
2011 Jun 22
2
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
On Jun 22, 2011, at 9:00 AM, Renato Golin wrote:
> On 22 June 2011 16:50, Jim Grosbach <grosbach at apple.com> wrote:
>>> This sounds like a dead end as newer binutils are GPLv3.
>>
>> Yeah, that's definitely a very real concern and a big motivation to get the MC based asm parser whipped into usable shape. We're much more in control of our own destiny then.
2013 Jun 26
1
[LLVMdev] Auxiliary operand types for disassembler.
...rder for the disassembler to correctly represent the insn it needs
>> to accumulate the series of insns that form the packet. Only when the
>> entire packet is known can the meaning of the parse bits be properly
>> interpreted.
>>
>> Changing objdump's interface to printInst so it passes the raw insn
>> bits down would allow the printer to accumulate the same information
>> and would work just as well I think.
>>
>> --
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> hosted by The Linux Foundation
>> <...
2018 Jun 30
2
Using BuildMI to insert Intel MPX instruction BNDCU failed
...orkspace/llvm/include/llvm/MC/MCInst.h:182:0
#11 0x00000000026695fd llvm::X86ATTInstPrinter::printOperand(llvm::MCInst
const*, unsigned int, llvm::raw_ostream&)
/home/shenyouren/workspace/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp:185:0
#12 0x0000000002664c06
llvm::X86ATTInstPrinter::printInstruction(llvm::MCInst const*,
llvm::raw_ostream&)
/home/shenyouren/workspace/build-llvm/lib/Target/X86/X86GenAsmWriter.inc:48204:0
#13 0x0000000002668edc llvm::X86ATTInstPrinter::printInst(llvm::MCInst
const*, llvm::raw_ostream&, llvm::StringRef, llvm::MCSubtargetInfo const&)
/home/shenyo...
2013 Sep 17
0
[LLVMdev] [patch] alias instruction for Intel syntax
...--git a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
index e7e7b15..b9f78a5 100644
--- a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
+++ b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
@@ -39,7 +39,8 @@ void X86IntelInstPrinter::printInst(const MCInst *MI,
raw_ostream &OS,
if (TSFlags & X86II::LOCK)
OS << "\tlock\n";
- printInstruction(MI, OS);
+ if (!printAliasInstr(MI, OS))
+ printInstruction(MI, OS);
// Next always print the annotation.
printAnnotation(OS, Annot);
-------------- next p...
2011 Jun 22
2
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
...or lots of the changes necessary to handle llvm assembly. Let's cross our fingers that's the case.
>
> --- a/contrib/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
> +++ b/contrib/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
> @@ -44,17 +44,18 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
> const MCOperand &MO2 = MI->getOperand(2);
> const MCOperand &MO3 = MI->getOperand(3);
>
> - O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
> + O << '\t'...
2013 Oct 10
0
[LLVMdev] [PATCH] R600/SI: Embed disassembly in ELF object
...;
> + std::string &DisasmLine = DisasmLines.back();
> + raw_string_ostream DisasmStream(DisasmLine);
> +
> + AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *TM.getInstrInfo(),
> + *TM.getRegisterInfo());
> + InstPrinter.printInst(&TmpInst, DisasmStream, StringRef());
> +
> + // Disassemble instruction/operands to hex representation.
> + SmallVector<MCFixup, 4> Fixups;
> + SmallVector<char, 16> CodeBytes;
> + raw_svector_ostream CodeStream(CodeBytes);
> +
> + MCOb...
2013 Oct 10
2
[LLVMdev] [PATCH] R600/SI: Embed disassembly in ELF object
Hi,
This patch adds R600/SI disassembly text to compiled object files, when
a code dump is requested, to assist debugging in Mesa clients.
Here's an example of the output in a Mesa client with a corresponding
patch and RADEON_DUMP_SHADERS set:
Shader Disassembly:
S_WQM_B64 EXEC, EXEC ; BEFE0A7E
S_MOV_B32 M0, SGPR6 ; BEFC0306
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...st.h"
>> #include "llvm/MC/MCInst.h"
>> #include "llvm/MC/MCAsmInfo.h"
>> #include "llvm/MC/MCExpr.h"
>> @@ -37,20 +38,50 @@ StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {
>>
>> void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream&O,
>> StringRef Annot) {
>> + printInst((const HexagonMCInst*)(MI), O, Annot);
>> +}
>> +
>> +void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream&O,
>> +...