search for: prera

...es, but the issue looks very similar to our first > >> experience with sched DAG constructor. > >> > >> Sergei > > Tom, > > The version of VLIWPacketizerList currently checked in was designed to work for postRA scheduling. I want it to be adapted for use in preRA (called by MachineScheduler), but Sergei and others are still engaged in that process. Since nothing is checked in yet, you'll be running into the same issues as Sergei. Ok, so I think I'll do a postRA packetizer for now and them come back to my preRA packetizer once VLIWPacketizerList can...

...>> Those are just my guesses, but the issue looks very similar to our first >> experience with sched DAG constructor. >> >> Sergei Tom, The version of VLIWPacketizerList currently checked in was designed to work for postRA scheduling. I want it to be adapted for use in preRA (called by MachineScheduler), but Sergei and others are still engaged in that process. Since nothing is checked in yet, you'll be running into the same issues as Sergei. To me, the definition of "isSchedulingBoundary" is "something the DAG builder cannot handle". If you loo...

...of instructions in the current packet (DFA), it closes the current bundle and advances to the next cycle. The non-interlocked nature of our processor forces the bundling logic to live with the scheduling logic. We cannot build bundles without the scoreboard. I also tried to build bundles as a preRA pass in order to reduce the register pressure (so the RA will take full advantage of the vliw architecture). I've ran into some problems such as the re-materialization one that we have discussed some time ago (http://llvm.1065342.n5.nabble.com/Instruction-bundles-before-RA-Rematerialization...

...code with tracing or step through in the debugger. Even though I've hacked on the code quite a bit, the interaction between the scheduler and target hooks is still not obvious to me from glancing at the code. FWIW, I'm hoping it can be cleaned up gradually, maybe for the next release. The preRA scheduler is bottom-up, for register pressure tracking. The postRA scheduler is top-down, for simpler hazard detection logic. On ARM, the preRA scheduler uses an unspecialized instance of ScoreboardHazardRecognizer. The machine-independent RecedeCycle() logic that operates on the scheduler itinera...

On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote: > Tom, > > I do not have your call stack, but packetizer calls > ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is > the first time you use the new MI sched infrastructure (like your target has > not implemented misched yet) there might be some work needed to implement > couple target

...description sounds fine to me. I assume you are totally decoupled from what LLVM currently calls the "postRA" scheduling pass. Hopefully you don't need anything in PostRASchedulerList.cpp. Running your bundler as a preEmit pass is the cleanest approach. But if need be, we can support preRA bundling at the time the MachineScheduler currently runs (if enabled). TargetPassConfig allows you to substitute your own pass in place of MachineScheduler. Passes that run after MachineScheduler are intended to support instruction bundles. This feature is not extensively tested, so anyone taking t...

...ulations: %1 = add i32 , i32 %2 = add i32 , i32 Occurrence Verification: - Machine Outliner At the post RA level you don’t need to do any kind of special verification for candidate occurrences because you don’t have to deal with the concept of inputs. - IR Outliner At the IR/preRA level we need to do complex verification to make sure that the occurrences within a candidate have the same internal inputs. If two occurrences have different internal inputs then we need some form of control flow to maintain correctness. By internal inputs I mean the operands of instructions that...

Hi, I'm working on a custom top-down post RA scheduler which builds bundles at the same time for our VLIW processor. I've borrowed most of the implementation from the resource priority queue implemented for the existent VLIW scheduler but applied to the context of MI scheduling. Basically, instructions that are likely to be bundled must be scheduled first (i.e. get higher priority).

..., i32 > > Occurrence Verification: > > - Machine Outliner > At the post RA level you don’t need to do any kind of special verification for candidate occurrences because you don’t have to deal with the concept of inputs. > > - IR Outliner > At the IR/preRA level we need to do complex verification to make sure that the occurrences within a candidate have the same internal inputs. If two occurrences have different internal inputs then we need some form of control flow to maintain correctness. By internal inputs I mean the operands of instructions that...

...special requirements during register allocation - there is both a need to handle register pairing and to never spill a flag result reg-class (which might happen at -O0 for no obvious reason). Since neither of these issues seems to be supported, I have tried to pre-allocate these registers in the preRA pass. This has resulted in "using undefined physical register" verification failure with the fast regalloc, as this regalloc does not scan the code properly for used pregs, and thus marks a use-physreg-op as 'Kill' when it is in fact used in the following instruction (where it was...

...i32 > > Occurrence Verification: > > - Machine Outliner > At the post RA level you don’t need to do any kind of special > verification for candidate occurrences because you don’t have to deal with > the concept of inputs. > > - IR Outliner > At the IR/preRA level we need to do complex verification to make sure > that the occurrences within a candidate have the same internal inputs. If > two occurrences have different internal inputs then we need some form of > control flow to maintain correctness. By internal inputs I mean the > operands o...

Andy, I should have been more clear, the ARM implementation has: void ARMHazardRecognizer::RecedeCycle() { llvm_unreachable("reverse ARM hazard checking unsupported"); } How does that work? Thanks again, Hal On Tue, 2011-11-29 at 09:47 -0800, Andrew Trick wrote: > ARM can reuse all the default scoreboard hazard recognizer logic such as recede cycle (naturally since its the

Hello everyone, I am working on some changes to the Hexagon VLIW PreRA scheduler, and as a part of it need to test aliasing properties of two instruction. What it boils down to is the following code: char a[20]; char s; char *p, *q; // p == &a[0]; q == &s; void test() { register char reg; s = 0; reg = p[0] + p[1]; s = q[0] + reg; return; } When...

...ge them, r1 should be changed to r0, and r2 to r1. Sometimes the same problem happens when the frame offset is misaligned, e.g. r0 will have offset aligned to word, not dword. Can someone please point me out in which direction should I move? And also - at which step should I apply such pass? If on PreRA - how to set reg constraints such as regsequence, as well as frame constraints? If before frame finalization - how to set frame constraints? If on pre-emit like i'm doing now - how to optimize and rewrite frame offsets and regs? Thanks, Petr -------------- next part -------------- An HTML att...

...atural to handle nop insertion within your implementation. > Nop insertion during scheduling sounds good to me, but nop insertion after regalloc has the advantage of being able to insert nops for spill/reload. Unless you don’t have spills? To elaborate a bit more, MachineScheduler can run both preRA and postRA. So, if you want to do nop insertion within MachineScheduler (as opposed to a separate pass) you could enable it only during postRA scheduling. -Andy > Pete >> >> In fact, the interpretation of most machine model properties (MircoOpBufferSize, resource BufferSize, Resou...

...rence Verification: >> >> - Machine Outliner >> At the post RA level you don’t need to do any kind of special verification for candidate occurrences because you don’t have to deal with the concept of inputs. >> >> - IR Outliner >> At the IR/preRA level we need to do complex verification to make sure that the occurrences within a candidate have the same internal inputs. If two occurrences have different internal inputs then we need some form of control flow to maintain correctness. By internal inputs I mean the operands of instructions that...

On Thu, Mar 1, 2012 at 1:04 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Hello everyone, > >  I am working on some changes to the Hexagon VLIW PreRA scheduler, and as a > part of it need to test aliasing properties of two instruction. > What it boils down to is the following code: > > char a[20]; > char s; > char *p, *q; // p == &a[0]; q == &s; > > void test() > { >  register char reg; > >  s = 0; &gt...

...ess >> instructions available) seems like a bad idea. > > I've worked on a few cpus in the past that had issue group > restrictions. It seems like a natural way to handle special kinds of > instructions. But I'm not aware of any LLVM backend that depends on it > for preRA scheduling. If they are, hopefully they're reading this and > will speak up. > > My thinking a few years back was that targets would only run post-RA > scheduling in rare cases and only for blocks with spill code, as a > spill-fixup pass. That's not what you, and probably...

ARM can reuse all the default scoreboard hazard recognizer logic such as recede cycle (naturally since its the primary client). If you can do the same with PPC that's great. Andy On Nov 29, 2011, at 8:51 AM, Hal Finkel <hfinkel at anl.gov> wrote: >> Thanks! Since I have to change PPCHazardRecognizer for bottom-up support >> anyway, is there any reason not to have it

...freedom of other heuristics (making less instructions available) seems like a bad idea. I've worked on a few cpus in the past that had issue group restrictions. It seems like a natural way to handle special kinds of instructions. But I'm not aware of any LLVM backend that depends on it for preRA scheduling. If they are, hopefully they're reading this and will speak up. My thinking a few years back was that targets would only run post-RA scheduling in rare cases and only for blocks with spill code, as a spill-fixup pass. That's not what you, and probably others are doing, so if you...