search for: preprocessiseldag

2015-07-08 17:58 GMT+02:00 escha <escha at apple.com>: > [...] > > If you want to “revert" this sort of thing, you can do it at Select() time > or PreprocessISelDAG(), which is what I did on an out-of-tree backend to > turn add X, -C into sub X, C on selection time. This still lets all the > intermediate optimizations take advantage of the canonicalization. > > —escha Unaware of your proposal, I used the TargetLowering::PerformDAGCombine hook. Is...

Dear all, I have been working on a new LLVM backend. Some instructions, like sub, can take an positive constante, encoded into 5 bits thus lower than 32, and a register, as operands. Unfortunately, DAGCombiner.cpp changes patterns like 'sub x, 5' into 'add x,-5'. Similarly, I found changes in some IR to IR passes, with no clear gain (at least not clear to me), and even penalty

...rnet.com> > Subject: Re: [LLVMdev] Prevention register promotion at the isel codegen phase > Date: 24 November 2012 17:09:58 GMT > To: Joseph Pusdesris <joe at pusdesris.com> > > I had a similar problem trying to implement reg-mem operations. The solution I chose was to use PreprocessISelDAG() to decide which operands needed spilling to memory and then to store and load them from a new stack slot. This seems to work OK for me, though I'm no expert in such matters - perhaps someone more knowledgeable could comment? > > Given that operand OpNo of Node needs to be a load, this...

...*Subject: **Re: [LLVMdev] Prevention register promotion at the isel > codegen phase* > *Date: *24 November 2012 17:09:58 GMT > *To: *Joseph Pusdesris <joe at pusdesris.com> > > I had a similar problem trying to implement reg-mem operations. The > solution I chose was to use PreprocessISelDAG() to decide which operands > needed spilling to memory and then to store and load them from a new stack > slot. This seems to work OK for me, though I'm no expert in such matters - > perhaps someone more knowledgeable could comment? > > Given that operand OpNo of Node needs to be...

Martin: It sounds like you are doing is more akin to shuffle selection than fusion and therefore it's a better fit for instruction selection than DAGCombining. Try movign it to <Target>ISelDAGToDAG's Select (or potentially PreprocessISelDAG). Th -Nirav On Tue, Mar 6, 2018 at 4:05 PM Martin J. O'Riordan <MartinO at theheart.ie> wrote: > We discovered what is happening. > > > > SDAGCombiner essentially looks at various combinations of nodes to do with > vectors, and when it can, it creates a vector shu...

We discovered what is happening. SDAGCombiner essentially looks at various combinations of nodes to do with vectors, and when it can, it creates a vector shuffle. The problem is, that our vector shuffle lowering builds new trees with vector element, or vector sub-vector insert sequences. The generic DAGCombiner, reconstructs these into a new shuffle, and so the loop continues - we reduce it,

I'm trying to write a tablegen pattern to that matches a sequence of SDNodes and emits again an SDNode and another instruction. The pattern I've written looks like the folowing: def : Pat<(foo (bar GPR:$rs1), simm12:$imm1), (bar (BAZ GPR:$rs1, simm12:$imm1))>; foo and bar are SDNodes, BAZ is an instruction. In particular, bar is defined as follows: def bar :

After removing CALL64m, the resulting DAG has a cycle that cannot be scheduled. I've attached a PDF of the DAG before instruction selection (-view-isel-dags), and after instruction select (-view-sched-dags). Notice how the flag/chain relationships between MOV64rm and CALL64r make it impossible to schedule. Here's the code being compiled: define ccc void @ArgsFree() nounwind { entry:

Greetings, LLVM devs, For the past few weeks, I have been putting together a 6502 backend for LLVM. The 6502 and its derivatives, of course, have powered countless microcomputers, game consoles and arcade machines over the past 40 years. The backend is just an experimental hobby project right now. The code is available here: <https://github.com/beholdnec/llvm-m6502>. This branch introduces