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...ll targets, making the zext free. When the zext *isn't* folded into a load, what you're really looking for is a code placement pass which tries to put the zexts in non-redundant (and non-partially redundant) places. This sort of code placement pass could be done at the LLVM IR level (as a prelegalization like you mention), it could be done as a pre-regalloc machine pass, or as a post-regalloc machine pass. The right answer depends on what and how much you care about this. If you're seeing fully redundant zexts, then I'd look into why machinecse isn't picking this up. If you&...

I'm looking at llvm-generated ARM code that has some unnecessary UXTB (zero extend) instructions, and it seems to me that doing type legalization as an entirely local transformation is not the best approach. I'm thinking in particular about legalizing integer types that need to be promoted to the target register size, i.e., i8 and i16 for ARM promoting to i32. Currently we sign-extend or

..., making the zext free. When the zext *isn't* folded into a load, what you're really looking for is a code placement pass which tries to put the zexts in non-redundant (and non-partially redundant) places. > > This sort of code placement pass could be done at the LLVM IR level (as a prelegalization like you mention), it could be done as a pre-regalloc machine pass, or as a post-regalloc machine pass. > > The right answer depends on what and how much you care about this. If you're seeing fully redundant zexts, then I'd look into why machinecse isn't picking this up...